2.2.1. Boot memory and clock speed configuration switch S8

The configuration switches S8-1 to S8-4 determine boot memory type.

Note

If the switch lever is down, the switch is ON. The default is OFF, switch lever up.

Table 2.1. Selecting the boot device

S8-4S8-3S8-2S8-1Memory device used as boot memory
OFFOFFOFFOFFNOR Flash 1 remapped to address 0x0.
OFF OFF OFF ONReserved.
OFF OFF ONOFF SRAM remapped to address 0x0 This is volatile memory and does not contain boot code.
OFF OFF ONONReserved.
OFF ONOFF OFF PISMO expansion memory selected by nCS1 is remapped to address 0x0.
OFF ONOFF ONPISMO expansion memory selected by nCS2 is remapped to address 0x0.
OFF ONONOFF PISMO expansion memory selected by nCS3 is remapped to address 0x0.
OFF ONONONPISMO expansion memory selected by nCS0 is remapped to address 0x0.
ONXXXRouting switches S8[3:1] are ignored and all accesses are placed on the tile site 2 master bus for slaves located in an attached Logic Tile.

The Boot Monitor remaps SDRAM to address 0x0. If you are not using the Boot Monitor, your OS loader or application must reset the memory remapping (see System Controller).

The default values for configuration switches S8-1 to S8-8 are listed in Table 2.2. For more information on configuration switch S8, see Test, configuration, and debug interfaces and the Application Note for the FPGA image and Core Tile that you are using.

Table 2.2. Default switch positions

SwitchDefaultFunction in default position
S8-1OFF

Selects NOR flash as boot memory, see Table 2.1.

S8-2OFF
S8-3OFF
S8-4OFF
S8-5OFF

Sets the default bus frequency:

  • ON selects 10MHz system clock, typically the ACLK and HCLK.

  • OFF selects the maximum frequency for the attached system, typically this is 25MHz for AHB systems or 30MHz for AXI systems.

S8-6 OFF

Reserved to override default system clock frequency. See the Application Note for your product configuration for more details.

The default selection typically bypasses the PLL and sets the bus to core ratio to 1:1.

S8-7OFF
S8-8OFF

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