2.3. Connecting a Core Tile

The baseboard does not include a processor. A processor must be added by:


The FPGA image must match the type and number of Core Tiles that are present on the baseboard.

Because the AHB and AXI buses use different pins, an incorrect FPGA configuration might result in damaged boards. To check the configuration:

  1. Set the CONFIG switch S1 to the OFF position.

  2. Power on the board.

  3. Check that the text displayed on the character LCD matches the Core Tile to add.

The FPGA images are included with the application notes on the supplied CD:

  • use AN152 for ARM11MPCore Core Tile

  • use AN148 for ARM7TDMI, ARM926EJ-S and ARM1136JF-S Core Tiles.

See Loading FPGA and PLD images, FPGA configuration, and the relevant application notes for more details.

One or two Core Tiles can be connected to the baseboard:

Press down firmly on the Core Tile to ensure that the connectors mate properly.

Figure 2.3. Core Tile mounted on tile site 1

Core Tile mounted on tile site 1

Figure 2.4. Multiprocessor system with two Core Tiles

Multiprocessor system with two Core Tiles

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