B.2. Clock frequency restrictions

The maximum clock frequencies that can be used for reliable operation depend on the Core Tiles or Logic Tiles fitted.


The ICS307 programmable oscillators OSC0, OSC1, OSC2, OSC3, and OSC4 can be programmed to deliver very high clock signals, 200MHz. The only Core Tile clock input that can function at or near this frequency is PLLCLKEXT (that is, an external clock input to the Core Tile with the PLL bypassed).

Also, the settings for VCO divider, output divider, and output select values are interrelated and must be set correctly. Some combinations of settings do not result in stable operation. For more information on the ICS clock generator and a frequency calculator, see the ICS web site.

See the application note for your system configuration for timing details.

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