3.11. Ethernet interface

The Ethernet interface is implemented with a SMC LAN9118 10/100 Ethernet single-chip MAC and PHY. This is provided with a interface to the static memory bus of the FPGA.

The internal registers of the LAN9118 are mapped onto the static memory bus and occupy 16 words starting at location 0x4E000000.

The isolating RJ45 connector incorporates two network status LEDs. The function of the LEDs can be set to indicate link, activity, transmit, receive, full duplex, or 10/100 selection. See the data sheet for the LAN9118 for more details on programming the registers.

The architecture of the Ethernet interface is shown in Figure 3.29. See also Figure 3.19.

Figure 3.29. Ethernet interface architecture

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Table 3.12. Ethernet signals

SignalDescription
SMDATA[31:0]Data lines to Ethernet controller from the SMC.
USBETHA[15:9]Address lines to USB and Ethernet controllers from the configuration PLD.
SMADDR[8:0]Address lines to Ethernet controller from the SMC.
ETHnBE[3:0]Byte-enable signals to Ethernet controller
TPO+, TPO-Signal from controller to Ethernet interface
TPI+, TPI-Signal from interface to controller
LEDA, LEDBActivity indicator LEDs. The function of the LEDs can be configured by writing to a LAN9118 register.
ETHRESETReset signal to LAN9118
ETHARDYAsynchronous ready signal
ETHnRDYRTNSignals to the controller to complete synchronous read cycles
ETHnADSLatches address to controller
ETHLCLKClock to controller interface
ETHnRDRead signal for asynchronous interface
ETHnWRWrite signal for asynchronous interface
ETHnDATACSEnables accesses to the controller data path
ETHnCYCLEUsed to control EISA burst mode synchronous cycles if LOW
ETHAENAddress valid signal to controller.
ETHnLDEVAsserted LOW if the address enable signal, ETHAEN, is low and the address lines decode to the controller address programmed into the base address register
ETHWnRDefines bus direction for synchronous accesses

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