3.22. USB interface

The FPGA provides the bus interface to an external Philips ISP1761 controller. Three USB interfaces are provided on the baseboard, see Figure 3.42. See also Figure 3.20 for an overview of how the USB controller is attached to the static-memory bus.

The internal registers of the controller are memory-mapped at 0x4F000000.

Figure 3.42. ISP1761 block diagram

ISP1761 block diagram

USB port 1 provides an OTG device interface and connects to J45. USB ports 2 and 3 can function in either master or slave mode and connect to the dual type A connector J46 (USB2 is the top connector).


The USB debug interface has a dedicated USB controller. See JTAG and USB debug port support.

The signals associated with the USB interfaces are shown in Table 3.20.

Table 3.20. USB interface signal assignment

Signal nameDirectionDescription
DPxBidirectionalD+ data line
DMxBidirectionalD- data line
SMDATA[31:0]BidirectionalData lines of USB controller
SMADDR[15:0]From FPGAAddress lines of USB controller
USBnCSFrom FPGAController chip select
USBnRDFrom FPGARead strobe to controller
USBnWRFrom FPGAWrite strobe to controller
USBnINTTo FPGAController interrupt out
USBnRESETFrom FPGAController reset
USBHCSUSPFrom FPGAGPIO2 in the FPGA drives this signal HIGH to wake up the host controller
USBDCSUSPFrom FPGAGPIO2 in the FPGA drives this signal HIGH to wake up the device controller
REFCLK12MHZ2UFrom FPGA24MHz reference clock to controller (this clock is not used and the 12MHz crystal output typically provides the reference clock)
nPO[3:1]From FPGASwitches 5V power to connectors
nOC[3:1]From USBOver current detect (disconnects power to connectors)
USBDRQ[1:0]From FPGADMA request. USBDRQ1 for channel 1, USBDRQ0 for channel 0.
USBDACK[1:0]To FPGADMA acknowledge. USBDACK1 for channel 1, USBEDACK0 for channel 0.


For a full description of the USB controller, refer to the data sheet for the Philips ISP1761.

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