2.4. Connecting a Logic Tile

The Logic Tiles, such as the LT-XC2V6000, enable developing AMBA AHB, AXI, and APB peripherals, or custom logic, for use with ARM cores.

Press down firmly on the Logic Tile to ensure that the connectors mate properly.

Note

The design in the Logic Tile FPGA must implement logic to handle the AHB or AXI bus signals from the baseboard. See the application notes supplied on the CD (and on the ARM web site) for more details on using Logic Tiles.

Figure 2.5 shows a Logic Tile mounted on the baseboard.

Figure 2.5. Logic Tile mounted in tile site 2

Logic Tile mounted in tile site 2

Use the JTAG interface on the baseboard to program the configuration flash in the Logic Tile or to directly load the Logic Tile FPGA image. For more information on JTAG signals, see JTAG and USB debug port support.

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