A PL111 PrimeCell CLCD controller is present in the FPGA.
A separate CLCD controller can be implemented in an attached Logic Tile. The peripheral switches (see CLCDC routing switches) control the routing from the CLCD controllers to the display interface logic and connectors.
The baseboard provides a display interface with outputs to:
a VGA connector for connecting a VGA or SVGA monitor
a CLCD adaptor board with CLCD, keypad, and touchscreen connectors. (See Appendix C LCD Kits for information on the touchscreen controller and the CLCD displays.)
A DAC re-arranges the CLCDC display signals for the selected resolution and color depth and converts the CLCD signals into VGA analog signals.
Use the Synchronous Serial Port (SSP) to access the touchscreen controller on the adapter board.
Figure 3.27 shows the architecture of the display interface.
See Color LCD Controller, CLCDC for interface details.
Table 3.10. Display interface signals
| Signal | Description |
|---|---|
| B[7:0] | Blue output signals to D/A converter and to or from the Logic Tile. A buffered version of these signals are output to the CLCD adaptor board as BUF_B[7:0]. |
| G[7:0] | Green output signals to D/A converter and to or from the Logic Tile. A buffered version of these signals are output to the CLCD adaptor board as BUF_G[7:0]. |
| R[7:0] | Red output signals to D/A converter and to or from the Logic Tile. A buffered version of these signals are output to the CLCD adaptor board as BUF_R[7:0]. |
| RED, GREEN, BLUE | Analog output from D/A converter for red, green, and blue signals to VGA connector. |
| VGA_HSYNC | The VGA horizontal synchronization signal. (This is a filtered version of LCD_CLLP.) |
| VGA_VSYNC | The VGA vertical synchronization signal (This is a filtered version of LCD_CLFP.) |
| VGA_M[1:0] | These signals select the VGA display resolution. The signals control remapping of the R[7:0], G[7:0], and B[7:0] data signals for the VGA display. |
| VGA_CLK | The VGA clock synchronizes the conversion of the B[7:0], G[7:0], and R[7:0] signals into the RED, GREEN, and BLUE analog signals. |
| nBLANK | The VGA video blanking signal. |
| TSSCLK | Clock to touchscreen controller. |
| TSMOSI | Data from touchscreen controller. |
| TSMISO | Data from touchscreen controller. |
| TSnDAV | Touchscreen controller data available signal. |
| TSnPENIRQ | Touchscreen controller pen down interrupt. |
| TSnKPADIRQ | Touchscreen controller key pressed interrupt. |
| TSnSS | Touchscreen controller chip select. |
| Power control | The nLCDIOON, CLPOWER, PWR3V5VSWITCH, VDDNEGSWITCH, and VDDPOSSWITCH signals can be used by the LCD adaptor board to select voltage for the display panel. Links on the board are set at manufacture to specify whether the panel voltages are fixed or programmable. |
| LCDID[4:0] | These signals are determined by resistor links on the LCD adaptor board. They indicate the type of display that is attached to the adaptor board. |
| LCDDATnCOM | This signal indicates to the external controller on the CLCD expansion board whether the current value is data or a command. |
| LCDSD0 | Serial data in or out for an external controller on the CLCD expansion board. |
| LCDSD0OUTnIN | This signal controls the direction of the serial data bus. |
| LCDXWR | Write signal to an external controller on the CLCD expansion board. |
| LCDXCS | Chip select signal to an external controller on the CLCD expansion board. |
| LCDXRD | Read signal to an external controller on the CLCD expansion board. |
| CLD[23:0] | LCD panel data. This is the digital RGB signals and synchronization signals. |
| CLCP | LCD panel clock. |
| CLLP | Line synchronization pulse (STN)/horizontal synchronization pulse (TFT). |
| CLFP | Frame pulse (STN)/vertical synchronization pulse (TFT). A buffered version of this signal is output to CLCD adaptor board as BUF_CLFP. |
| CLAC | STN AC bias drive or TFT data enable output. A buffered version of this signal is output to the CLCD adaptor board as BUF_CLAC. |
| CLLE | Line end signal. A buffered version of this signal is output to the CLCD adaptor board as BUF_CLLE. This signal can also be driven to the Logic Tile on LT_CLLE. |
| CLPOWER | LCD panel power enable. Depending on the link settings on the CLCD adaptor board, this signal can be used to turn off power to the display. |
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