3.21. UART interface

Four UARTs (SER0, SER1, SER2, and SER3) are implemented with PL011 PrimeCells incorporated into the baseboard FPGA.

The UARTs have the following features:

Signals from UART0, UART1, and UART2 are also connected to the peripheral switches for the tile sites as shown in Figure 3.39.

Figure 3.39. UARTs block diagram

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The signals from the FPGA are converted from logic level to RS232 level by MAX3243E buffers as shown in Figure 3.40 and Figure 3.41.

Figure 3.40. UART0 interface

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Figure 3.41. Simplified interface for UART[3:1]

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See also UART and the ARM PrimeCell UART (PL011) Technical Reference Manual.

Zero Ohm resistor links connect DTR to DSR for the following ports:

The signals associated with the UART interface are shown in Table 3.19.

Table 3.19. Serial interface signal assignment

Signal Description
SERx_TXDTransmit data
SERx_RTSReady to send
SERx_DTR[a]Data terminal ready
SERx_CTSClear to send
SERx_DSRaData set ready
SERx_DCDaData carrier detect
SERx_RXDReceive data
SERx_RIaRing indicator

[a] For UART1, UART2, and UART3, the DTR and DSR signals are connected together and are not input to the FPGA. Also, the DCD and RI signals are not connected to the FPGA


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