RealView Emulation Baseboard User Guide (Lead Free): 3.21. UART interface

3.21. UART interface

Four UARTs (SER0, SER1, SER2, and SER3) are implemented with PL011 PrimeCells incorporated into the baseboard FPGA.

The UARTs have the following features:

functionally similar to standard 16C550 devices
port function corresponds to the DTE configuration
SER0 (UART0) has full CTS, RTS, DCD, DSR, DTR, and RI modem control signals
SER1, SER2, and SER3 (UART1, UART2, and UART3) have simple modem control signals CTS and RTS
programmable baud rates of up to 1.5Mbits per second (the line drivers however, are only guaranteed to 250kbps)
16-byte transmit FIFO
16-byte receive FIFO
programmable interrupt.

Signals from UART0, UART1, and UART2 are also connected to the peripheral switches for the tile sites as shown in Figure 3.39.

Figure 3.39. UARTs block diagram

The signals from the FPGA are converted from logic level to RS232 level by MAX3243E buffers as shown in Figure 3.40 and Figure 3.41.

Figure 3.40. UART0 interface

Figure 3.41. Simplified interface for UART[3:1]

See also UART and the ARM PrimeCell UART (PL011) Technical Reference Manual.

Zero Ohm resistor links connect DTR to DSR for the following ports:

The signals associated with the UART interface are shown in Table 3.19.

Table 3.19. Serial interface signal assignment

Signal	Description
SERx_TXD	Transmit data
SERx_RTS	Ready to send
SERx_DTR^[a]	Data terminal ready
SERx_CTS	Clear to send
SERx_DSR^a	Data set ready
SERx_DCD^a	Data carrier detect
SERx_RXD	Receive data
SERx_RI^a	Ring indicator
^[a]For UART1, UART2, and UART3, the DTR and DSR signals are connected together and are not input to the FPGA. Also, the DCD and RI signals are not connected to the FPGA

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