3.2.1. FPGA configuration

At power-up the FPGA loads its configuration data from one of two images stored in a flash memory device. Parallel data from the flash memory is streamed by the configuration PLD into the configuration ports of the FPGA. Figure 3.11 and Figure 3.13 show the FPGA configuration mechanism. The image loaded into the FPGAs is determined by the configuration switch as listed in FPGA image select switch.

Figure 3.11. FPGA configuration

FPGA configuration


The configuration flash is a separate device and not part of the user NOR flash. The configuration flash can be accessed through the SMC static memory space, but this is not recommended because the contents might be corrupted.

The baseboard is shipped with a test image in the configuration flash. You must load a new image into the configuration flash before you can use the development board. For details on loading an image, see Loading FPGA and PLD images. The FPGA configuration to load depends on the type and combination of tiles attached.


The 1.5V cell battery provides the VBATT backup voltage to the external DS1338 time-of-year clock and FPGA encryption key circuitry within the FPGA. Removing the battery erases the encryption key.

Each board is provided with an encryption key that is unique to the board. The standard image supplied with the board is not encrypted. However, encrypted images might be supplied by ARM in the future. If you are using encrypted images and the key is erased, you must return the board to ARM to have the key reloaded.

The battery is expected to last for approximately 10 years from manufacture of the baseboard. To replace the battery:

  1. Power on the baseboard. If the battery is removed while the board is powered down, the encryption key will be erased.

  2. Remove the old battery.

  3. Insert the new battery and ensure that the positive terminal is facing upwards in the holder.

Copyright © 2005-2011 ARM Limited. All rights reserved.ARM DUI 0411D