3.19. Synchronous Serial Port, SSP

The baseboard FPGA contains a PL022 PrimeCell SSP controller. Use the expansion connector J32 to connect to the SSP. The FPGA controls the SSP peripheral chip select, SSPnCS, as shown in Figure 3.37. The SSP signals are shared with the tiles sites and CLCD adaptor board.

Figure 3.37. SSP block diagram

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Table 3.18. SSP signal descriptions

Name

Description

SSPnCS

Chip select to external device connected to SSP controller.

SSPFSSOUT

PrimeCell SSP frame or slave select output (master).

SSPCLKOUT

PrimeCell SSP clock output (master).

SSPRXD

PrimeCell SSP receive data input.

SSPTXD

PrimeCell SSP transmit data output.

nSSPCTLOE

Output enable signal (active LOW) for the SSPCLKOUT output from the PrimeCell SSP. This output is asserted (LOW) when the device is in master mode and de-asserted (HIGH) when the device is in slave mode.

SSPFSSIN

PrimeCell SSP frame input (slave).

SSPCLKIN

PrimeCell SSP clock input (slave).

nSSPOE

Output enable signal (active LOW) to indicate when SSPTXD is valid.


The SSP functions as a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following:

Use the SSP controller to access:

See also Synchronous Serial Port, SSP and the ARM PrimeCell Synchronous Serial Port Controller (PL022) Technical Reference Manual.

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