3.18. Smart Card interface, SCI

The baseboard FPGA contains a PrimeCell Smart Card Interface (SCI).

There are two types of Smart Card connector that can be fitted to the board:

Figure 3.36 shows the tristate buffers that are used to provide the interface between the SCI and the smart card. The 16-way box header J28 enables you to monitor the signals or to connect an off-board smart card connector.

SCI output signals go to both the Logic Tile connectors and the Smart Card connector.

You can set the Smart Card interface voltage to operate at 5V, 3.3V or 1.8V by setting jumpers on J27.

The default setting is linking pins AB. Both 3.3V and 5V cards will function with this setting.


The Smart Card VCC is switched on and off by the SCIVCCEN signal from the PrimeCell.

See also Smart Card Interface, SCI and the SCI PrimeCell PL131 Technical Reference Manual.

Figure 3.36. SCI block diagram

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.17. Smart Card interface signals

SCICLKINPrimeCell SCI clock input.
nSCICLKENTristate output buffer control for clock (active LOW).
SCICLKOUTClock output.
nSCIDATAENTristate control for external off-chip buffer (active LOW).
SCIDATAINPrimeCell SCI serial data input.
nSCIDATAOUTENData output enable (typically drives an open-drain configuration, active LOW).
nSCICARDRSTReset to card (active LOW).
SCIFCBFunction code bit, used in conjunction with nSCICARDRST.
nSCIDETCard detect signal from card interface device (active LOW).
SC_CLKSmart Card clock (bidirectional)
SC_VCCProgrammable output voltage to connector and level translator
SCIDATABidirectional data signal to level translator
SC_IOBidirectional data signal from level translator to connector

Copyright © 2005-2011 ARM Limited. All rights reserved.ARM DUI 0411D