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Home > Hardware Description > Smart Card interface, SCI |
The baseboard FPGA contains a PrimeCell Smart Card Interface (SCI).
There are two types of Smart Card connector that can be fitted to the board:
J31 is a small connector. This connector is not installed at manufacture.
J33 is a large connector with a card detect switch. This connector is installed at manufacture.
Figure 3.36 shows the tristate buffers that are used to provide the interface between the SCI and the smart card. The 16-way box header J28 enables you to monitor the signals or to connect an off-board smart card connector.
SCI output signals go to both the Logic Tile connectors and the Smart Card connector.
You can set the Smart Card interface voltage to operate at 5V, 3.3V or 1.8V by setting jumpers on J27.
connect pins AB for 3.3V operation
connect pins CB for 5V operation
omit the link for 1.8V operation.
The default setting is linking pins AB. Both 3.3V and 5V cards will function with this setting.
The Smart Card VCC is switched on and off by the SCIVCCEN signal from the PrimeCell.
See also Smart Card Interface, SCI and the SCI PrimeCell PL131 Technical Reference Manual.
Table 3.17. Smart Card interface signals
Signal | Description |
---|---|
SCICLKIN | PrimeCell SCI clock input. |
nSCICLKEN | Tristate output buffer control for clock (active LOW). |
SCICLKOUT | Clock output. |
nSCIDATAEN | Tristate control for external off-chip buffer (active LOW). |
SCIDATAIN | PrimeCell SCI serial data input. |
nSCIDATAOUTEN | Data output enable (typically drives an open-drain configuration, active LOW). |
nSCICARDRST | Reset to card (active LOW). |
SCIFCB | Function code bit, used in conjunction with nSCICARDRST. |
nSCIDET | Card detect signal from card interface device (active LOW). |
SC_CLK | Smart Card clock (bidirectional) |
SC_VCC | Programmable output voltage to connector and level translator |
SCIDATA | Bidirectional data signal to level translator |
SC_IO | Bidirectional data signal from level translator to connector |