3.13. Interrupts

The baseboard FPGA contains four Generic Interrupt Controllers (GICs) as shown in Figure 3.31. The GICs handle the nFIQ and nIRQ interrupts to tile site 1 and tile site 2:

GIC1

generates the nIRQ interrupt for tile site 1

GIC2

generates the nFIQ interrupt for tile site 1

GIC3

generates the nIRQ interrupt for tile site 2

GIC4

generates the nFIQ interrupt for tile site 2.

All four interrupt controllers are connected to the interrupt requests outputs from the FPGA devices, external peripherals, the PCI expansion bus, and the PISMO memory expansion bus

Tile site 1 interrupt requests (other than COMMRX and COMMTX) Tile are driven by the EB, the actual signals used are dependant on the application note.

Tile site 2 interrupt requests (other than COMMRX and COMMTX) connect to all four GICs on the EB, the actual signals used are dependant on the application note.

Note

Refer to the appropriate Application Note for details of the supported interrupt interconnect when using a particular EB and Core Tile combination.

The interrupt masking must be set so that only one interrupt is generated for an interrupt request.

For details on the programming model for the interrupt controllers and the interrupt assignments, see Interrupt controller registers.

Figure 3.31. Interrupt controllers for tile site 1 and 2

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