3.16. PCI interface

The Xilinx PCI subsystem enables you to use the baseboard in a PC or to use third-party PCI expansion cards with the baseboard and the PCI enclosure.

PCI bridges pass valid accesses between the baseboard and the PCI bus. The PCI interface supports 5V and 3.3V PCI buses. The baseboard functions as a PCI daughter-card, that is it does not generate clocks but uses external clocks from the PCI enclosure.

The FPGA bus matrix recognizes addresses 0x60000000 to 0x6FFFFFFF as being intended for a target within the PCI address space of the memory map, and passes accesses within this region to the PCI bus. The PCI_IMAPx registers define the address translation values for the PCI I/O, PCI configuration, and PCI memory windows.

The PCI_SMAPx registers define the address translation values for PCI accesses to the FPGA internal bus.

The AHB to PCI bridge supports read and write accesses in both directions, as shown in Figure 3.34.

Caution

The PCI controller is provided by Xilinx. The source HDL for this device is not provided on the CD. See the Xilinx web site for more information on the PCI controller.

The PCI controller will be deleted if you rebuild the FPGA image.

See Appendix D PCI Backplane and Enclosure and PCI controller.

Figure 3.34. PCI bridge

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Note

The EB cannot generate an interrupt to the PCI bus.

This is a departure from the PCI bus specification.

Copyright © 2005-2011 ARM Limited. All rights reserved.ARM DUI 0411D
Non-Confidential