4.10. Ethernet

The Ethernet interface is implemented in an external SMC LAN9118 10/100 Ethernet single-chip MAC and PHY. The internal registers of the LAN9118 are memory-mapped onto the static memory bus and occupy 16 word locations at 0x4E000000.

Table 4.43. Ethernet implementation

PropertyValue
Location Board (LAN9118 chip)
Memory base address0x4E000000 (mapped onto the SMC bus)
Interrupt 28
DMANone, use memory to memory DMA to access the buffer memory. The master interface located in the LAN9118 is not supported.
Release versionThe FPGA contains a custom interface to the LAN9118 chip
Reference documentationLAN9118 Data Sheet (see also Ethernet interface).

To access the PHY MII registers, you must implement a synchronous serial connection in software to control the management register in Bank 3. By default, the PHY is set to isolate in the control register. This disables the external interface. Refer to the LAN9118 application note or to the self test program supplied on the CD for additional information.

When manufactured, an ARM value for the Ethernet MAC address and the register base address are loaded into the EEPROM. The register base address is 0. The MAC address is unique, but can be reprogrammed if required. Reprogramming of the EEPROM is done through Bank 1 (general and control registers). See About the SMSC LAN9118 for more information on programming the EEPROM.

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