4.17. Two-wire serial bus interface

A two-wire serial bus interface is implemented in the FPGA. The registers shown in Table 4.66 control the serial bus and provides access to control signals on the two memory expansion boards and to the time-of-year clock.

Table 4.65. Serial bus implementation

Location FPGA
Memory base address0x10002000
Interrupt NA
Release versionCustom logic
Reference documentationTwo-wire serial bus interface, Appendix E PISMO Memory Expansion Boards, and the data sheet for the Dallas Maxim DS1338 Real Time Clock.

Table 4.66. Serial bus register


Read serial control bits:

Bit [0] is SCL

Bit [1] is SDA


Set serial control bits:

Bit [0] is SCL

Bit [1] is SDA


Clear serial control bits:

Bit [0] is SCL

Bit [1] is SDA


SDA is an open-collector signal that is used for sending and receiving data. Set the output value HIGH before reading the current value.

Software must manipulate the SCL and SDA bits directly to access the data in the three devices. The pre-defined eight-bit device addresses are listed in Table 4.67. See the \firmware\examples directory on the CD for example code for reading the EEPROM that is on the memory expansion board.

Table 4.67. Serial bus device addresses

DeviceWrite addressRead address
Dynamic expansion E2PROM0xA00xA1
Static expansion E2PROM0xA20xA3
Time-of-year clock0xD00xD1

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