RealView Emulation Baseboard User Guide (Lead Free): 4.17. Two-wire serial bus interface

4.17. Two-wire serial bus interface

A two-wire serial bus interface is implemented in the FPGA. The registers shown in Table 4.66 control the serial bus and provides access to control signals on the two memory expansion boards and to the time-of-year clock.

Table 4.65. Serial bus implementation

Property	Value
Location	FPGA
Memory base address	`0x10002000`
Interrupt	NA
DMA	NA
Release version	Custom logic
Reference documentation	Two-wire serial bus interface, Appendix E PISMO Memory Expansion Boards, and the data sheet for the Dallas Maxim DS1338 Real Time Clock.

Table 4.66. Serial bus register

Address Name Access Description

Address	Name	Access	Description
`0x10002000`	SB_CONTROL	Read	Read serial control bits: Bit [0] is SCL Bit [1] is SDA
`0x10002000`	SB_CONTROLS	Write	Set serial control bits: Bit [0] is SCL Bit [1] is SDA
`0x10002004`	SB_CONTROLC	Write	Clear serial control bits: Bit [0] is SCL Bit [1] is SDA

0x10002000

SB_CONTROL

Read

Read serial control bits:

Bit [0] is SCL

Bit [1] is SDA

0x10002000

SB_CONTROLS

Write

Set serial control bits:

Bit [0] is SCL

Bit [1] is SDA

0x10002004

SB_CONTROLC

Write

Clear serial control bits:

Bit [0] is SCL

Bit [1] is SDA

Note

SDA is an open-collector signal that is used for sending and receiving data. Set the output value HIGH before reading the current value.

Software must manipulate the SCL and SDA bits directly to access the data in the three devices. The pre-defined eight-bit device addresses are listed in Table 4.67. See the \firmware\examples directory on the CD for example code for reading the EEPROM that is on the memory expansion board.

Table 4.67. Serial bus device addresses

Device	Write address	Read address
Dynamic expansion E2PROM	`0xA0`	`0xA1`
Static expansion E2PROM	`0xA2`	`0xA3`
Time-of-year clock	`0xD0`	`0xD1`

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