4.1. Memory map

The memory map is divided with sections assigned to the system, Core Tiles and Logic Tiles as shown in Table 4.1.

Table 4.1. System memory map

OwnerAddress rangeBus typeMemory region size
System FPGA0x00000000- 0x0FFFFFFFExternal or Internal256MB
System FPGA0x10000000- 0x100FFFFFInternal only1MB
Reserved0x10100000- 0x103FFFFFExternal only3MB
System FPGA0x10400000- 0x17FFFFFFInternal only124MB
Logic Tile site 10x18000000- 0x1FFFFFFFExternal only128MB
Reserved0x20000000- 0x3FFFFFFFExternal only512MB
System FPGA0x40000000- 0x7FFFFFFFInternal only1GB
Logic Tile site 20x80000000- 0xFFFFFFFFExternal only2GB

Note

The memory region 0x00000000-0x0FFFFFFF can be mapped to:

  • internal decode logic for access by the dynamic or static memory controller

  • the external AXI or AHB bus for decode by an external device on the tile sites.

The other memory regions have fixed decoding and are handled either internally or externally.

The locations for memory, peripherals, and controllers for the standard FPGA image are listed in Table 4.2 and Figure 4.1.

Table 4.2. Memory map for standard peripherals

PeripheralAddress rangeBus typeRegion size

Dynamic memory.

During boot remapping however, the bottom 64MB of this memory region can be:

  • NOR flash

  • static expansion memory

  • memory on the external AXI or AHB bus (slave fitted on tile site 2).

0x00000000-0x0FFFFFFFAHB or AXI256MB
System registers0x10000000-0x10000FFFAPB4KB
System controller0x10001000-0x10001FFFAPB4KB
Two-Wire Serial Bus Interface0x10002000-0x10002FFFAPB4KB
Reserved0x10003000-0x10003FFFAPB4KB
Advanced Audio CODEC Interface0x10004000-0x10004FFFAPB4KB
MultiMedia Card Interface (MCI)0x10005000-0x10005FFFAPB4KB
Keyboard/Mouse Interface 0 0x10006000-0x10006FFFAPB4KB
Keyboard/Mouse Interface 10x10007000-0x10007FFFAPB4KB
Character LCD Interface0x10008000-0x10008FFFAPB4KB
UART 0 Interface

0x10009000-0x10009FFF

APB4KB
UART 1 Interface

0x1000A000-0x1000AFFF

APB4KB
UART 2 Interface

0x1000B000-0x1000BFFF

APB4KB
UART 3 Interface

0x1000C000-0x1000CFFF

APB4KB
Synchronous Serial Port Interface

0x1000D000-0x1000DFFF

APB4KB
Smart Card Interface0x1000E000-0x1000EFFFAPB4KB
Reserved0x1000F000-0x1000FFFFAPB4KB

Watchdog Interface

0x10010000-0x10010FFF

APB4KB

Timer modules 0 and 1 interface

(Timer 1 starts at 0x10011020)

0x10011000-0x10011FFF

APB4KB

Timer modules 2 and 3 interface

(Timer 3 starts at 0x10012020)

0x10012000-0x10012FFF

APB4KB

GPIO Interface 0

0x10013000-0x10013FFF

APB4KB

GPIO Interface 1

0x10014000-0x10014FFF

APB4KB

GPIO Interface 2 (miscellaneous onboard I/O)

0x10015000-0x10015FFF

APB4KB
Reserved

0x10016000-0x10016FFF

APB4KB

Real Time Clock Interface

0x10017000-0x10017FFF

APB4KB
Dynamic Memory Controller configuration

0x10018000-0x10018FFF

APB4KB

PCI controller configuration registers

0x10019000-0x10019FFFAHB4KB
Reserved 0x1001A000-0x1001FFFFAPB24KB

Color LCD Controller

0x10020000-0x1002FFFFAHB64KB

DMA Controller configuration registers

0x10030000-0x1003FFFFAHB64KB

Generic Interrupt Controller 1 (nIRQ for tile 1)

0x10040000-0x1004FFFFAHB64KB

Generic Interrupt Controller 2 (nFIQ for tile 1)

0x10050000-0x1005FFFFAHB64KB

Generic Interrupt Controller 3 (nIRQ for tile 2)

0x10060000-0x1006FFFFAHB64KB

Generic Interrupt Controller 4 (nFIQ for tile 2)

0x10070000-0x1007FFFFAHB64KB

Static Memory Controller configuration registers

0x10080000-0x1008FFFFAHB64KB
Reserved

0x100A0000-0x100EFFFF

AHB448MB
Debug Access Port (DAP) ROM table Some debuggers read information on the target processor and the debug chain from the DAP table. This region might be unused on some baseboard variants. 0x10090000-0x100FFFFFAHB64KB
Reserved

0x10100000-0x103FFFFF

-3MB
Reserved

0x10400000-0x17FFFFFF

AHB or AXI124MB
Tile site 1 expansion If a tile is not fitted, the baseboard aborts accesses to this memory region

0x18000000-0x1FFFFFFF

AHB or AXI128MB
Reserved

0x20000000-0x3FFFFFFF

-512MB

SMC Chip Selects:

  • CS0 NOR flash (nNOR_CS1) 0x40000000-0x43FFFFFF

  • CS1 NOR flash (nNOR_CS2) 0x44000000-0x47FFFFFF

  • CS2 SRAM (nSRAMCS) 0x48000000-0x4BFFFFFF

  • CS3 (nSTATICCS3 and configuration PLD decoding)

    Config flash 0x4C000000-0x4DFFFFFF

    Ethernet 0x4E000000-0x4EFFFFFF

    USB 0x4F000000-0x4FFFFFFF

  • CS4 (nEXPCS) PISMO (nCS0) 0x50000000-0x53FFFFFF

  • CS5 (nSTATICCS4) PISMO (nCS1) 0x54000000-0x57FFFFFF

  • CS6 (nSTATICCS5) PISMO (nCS2) 0x58000000-0x5BFFFFFF

  • CS7 (nSTATICCS6) PISMO (nCS3) 0x5C000000-0x5FFFFFFF

  • CS8 (nSTATICCS7) PISMO (nCS4) reserved (tied HIGH)

0x40000000-0x5FFFFFFFAHB or AXI512MB

PCI interface bus windows

  • PCI SelfCfg window:  0x61000000-0x61FFFFFF
    
  • PCI Cfg window:      0x62000000-0x62FFFFFF
    
  • PCI I/O window:      0x63000000-0x63FFFFFF
    
  • PCI memory window 0: 0x64000000-0x67FFFFFF
    
  • PCI memory window 1: 0x68000000-0x6BFFFFFF
    
  • PCI memory window 2: 0x6C000000-0x6FFFFFFF
    
0x60000000-0x6FFFFFFFAHB or AXI752MB
Dynamic memory (mirror)0x70000000-0x7FFFFFFFAHB or AXI256MB
Tile site 2 expansion If a tile is not fitted, the baseboard aborts accesses to this memory region0x80000000-0xFFFFFFFFAHB or AXI2GB

Figure 4.1 shows an overview of the memory map.

Figure 4.1. System memory map for standard peripherals

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