4.15. PCI controller

The PCI controller is implemented in the FPGA and controls the interface to the PCI bus.

Table 4.52. PCI controller implementation

Location FPGA
Memory base address

0x10019000 for the map and control registers

0x60000000 for PCI configuration, I/O, and memory

The memory base for PCI master usage is configurable


48 PCI0

49 PCI1

50 PCI2

51 PCI3


The EB cannot generate an interrupt to the PCI bus.

This is a departure from the PCI bus specification.

DMANone. Memory to memory transfers can be set up in the DMAC.
Release versionCustom logic (Xilinx LogiCore DO-DI-PCI-AL)
Reference documentation

PCI v2.2 Specification (see the PCI SIG web site at www.pcisig.com) and the PCI section on the Xilinx web site.

See also Table 4.54, PCI interface, and Appendix D PCI Backplane and Enclosure)

The PCI slave bridge connected to the FPGA recognizes addresses 0x60000000 to 0x6FFFFFFF as being intended for a target within the PCI address space of the memory map, and passes accesses within this region to the PCI bus.

The windows that provide access to the PCI expansion bus are listed in Table 4.53.

Table 4.53. PCI bus memory map

PCI self config16MB0x60000000-0x60FFFFFF
PCI config16MB0x61000000-0x61FFFFFF
PCI I/O region16MB



I/O accesses from the baseboard are output on the PCI bus with addresses 0x00000000-0x00FFFFFF

PCI memory region 016MB0x63000000-0x63FFFFFF
PCI memory region 164MB0x64000000-0x67FFFFFF
PCI memory region 2 128MB0x68000000-0x6FFFFFFF

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