4.3.18. Peripheral I/O select, SYS_IOSEL

Table 4.21 lists the I/O devices that can be routed to either the FPGA, tile site1, or tile site 2. The SYS_IOSEL register (at 0x10000070) controls the state of the switches. A serial interface in the FPGA transmits the control signals to the routing PLD. The routing PLD outputs the individual control signals, nENT1_1 for example, to the electronic switches.

See Table 4.22 for more detail on the mapping between switch state and the values of the control bits.


The baseboard FPGA monitors these signals and if either tile site is selected to drive these I/O signals it will tri-state its drivers for those I/O signals.

Figure 4.12. SYS_IOSEL

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Table 4.21. Peripheral select signals

I/O deviceBitsAccessResetNote
Reserved[31]--Reserved for future use
Bank select[30]Read/Writeb0Selects between FPGA and tile as source of CLCD signals to CLCD logic and VGA connector.
T1 T2 sideband [29:26]Read/Writeb0000Controls sideband signals between tile site 1 and tile site 2. See Bus signals on headers.

The GPIOs are controlled separately to enable more complex interconnection.

SCI and KMI1[19:18]Read/Writeb00 
AACI and KMI0 [17:16]Read/Writeb00


MCICLK is included in this bank.

UART0[9:8]Read/Writeb00UART0 has more control signals than UART1/2.
CLCD[7:0]Read/Writeb00000000 Routing for CLCD signal groups.

Table 4.22. Peripheral routing signals

Control signalsSYS_IOSEL bitsInterconnected signalsPeripheral
nENT2_0[1:0] = b01T2Z[7:0]PERIPH[7:0]CLCD
nENT1_0[1:0] = b10T1Z[7:0]PERIPH[7:0]
nENT1T2_0[1:0] = b11T1Z[7:0]T2Z[7:0]
nENT2_1[3:2] = b01T2Z[15:8]PERIPH[15:8]
nENT1_1[3:2] = b10T1Z[15:8]PERIPH[15:8]
nENT1T2_1[3:2] = b11T1Z[15:8]T2Z[15:8]
nENT2_2[5:4] = b01T2Z[23:16]PERIPH[23:16]
nENT1_2[5:4] = b10T1Z[23:16]PERIPH[23:16]
nENT1T2_2[5:4] = b11T1Z[23:16]T2Z[23:16]
nENT2_3[7:6] = b01T2Z[31:24]PERIPH[31:24]
nENT1_3[7:6] = b10T1Z[31:24]PERIPH[31:24]
nENT1T2_3[7:6] = b11T1Z[31:24]T2Z[31:24]
nENT1_4[9:8] = b10T1Z[39:32]PERIPH[39:32]UART0
nENT2_4[9:8] = b01T2Z[39:32]PERIPH[39:32]
nENT1T2_4[9:8] = b11T1Z[39:32]T2Z[39:32]
nENT1_5[11:10] = b10T1Z[47:40]PERIPH[47:40]

UART1 on PERIPH[43:40]

UART2 on PERIPH[47:44]

nENT2_5[11:10] = b01T2Z[47:40]PERIPH[47:40]
nENT1T2_5[11:10] = b11T1Z[47:40]T2Z[47:40]
nENT1_6[13:12] = b10T1Z[55:48]PERIPH[55:48]SSP
nENT2_6[13:12] = b01T2Z[55:48]PERIPH[55:48]
nENT1T2_6[13:12] = b11T1Z[55:48]T2Z[55:48]
nENT1_7[15:14] = b10T1Z[63:56]PERIPH[63:56]



MCICLK is in bank 8

nENT2_7[15:14] = b01T2Z[63:56]PERIPH[63:56]
nENT1T2_7[15:14] = b11T1Z[63:56]T2Z[63:56]
nENT1_8[17:16] = b10T1Z[71:64]PERIPH[71:64]


AACI on PERIPH[69:65]

KMI0 on PERIPH[71:70]

nENT2_8[17:16] = b01T2Z[71:64]PERIPH[71:64]
nENT1T2_8[17:16] = b11T1Z[71:64]T2Z[71:64]
nENT1_9[19:18] = b10T1Z[79:72]PERIPH[79:72]

KMI1 on PERIPH[73:72]

SCI on PERIPH[79:74]

nENT2_9[19:18] = b01T2Z[79:72]PERIPH[79:72]
nENT1T2_9[19:18] = b11T1Z[79:72]T2Z[79:72]
nENT1_10[22:20] = b1xxT1Z[87:80]PERIPH[87:80]


nENT2_10[22:20] = bx1xT2Z[87:80]PERIPH[87:80]
nENT1T2_10[22:20] = bxx1T1Z[87:80]T2Z[87:80]
nENT1_11[25:23] = b1xxT1Z[95:88]PERIPH[95:88]


nENT2_11[25:23] = bx1xT2Z[95:88]PERIPH[95:88]
nENT1T2_11[25:23] = bxx1T1Z[95:88]T2Z[95:88]
nENT1T2_A[26] = b0T1Z[103:96]T2Z[103:96]

Sideband signals between tile site 1 and tile site 2. (There is no connection between these signals and any I/O on the board.)

0 T1Z is not connected to T2Z

1 T1Z is connected to T2Z

nENT1T2_B[27] = b0T1Z[111:104]T2Z[111:104]
nENT1T2_C[28] = b0T1Z[119:112]T2Z[119:112]
nENT1T2_D[29] = b0T1Z[127:120]T2Z[127:120]
nSWBANKCTL[30] = b0FPGA CLCD signals R[7:0], G[7:0], B[7:0], and CLCD timing and power control signalsSelects between FPGA and tile as source of CLCD signals to CLCD logic and VGA connector.
SWBANKCTL[30] = b1PERIPH[31:0] (from tile switches)

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