4.3.19. SYS_PLDCTL[2:1]

These registers (at 0x10000074 and 0x10000078) are used to control configuration of the PLD located on the Core Tiles.

Note

SYS_PLDCTL1 at 0x10000074 is used for tile site 1 and SYS_PLD2 at 0x10000078 is used for tile site 2.

The function of these registers might be different for the combination of boards that you are using. Read the application note for your system for any changes to this register area.

Table 4.9 lists the bit assignments for the PLD configuration registers.

Table 4.23. Core PLD control register, SYS_PLDCTL bit assignment

Bits

Access

Description

[31:11]

Reserved. Use read-modify-write to preserve value.

[10]

Read-only

PGOOD signal

[9:4]

Read/Write

CLKSEL

Bit 4:

0 = drive from below
1 = drive from above.

Bit 6:5:

b00 = CLK_NEG_UP/DN_IN
b01 = X[32]
b10 = GND
b11 = GLOBALCLK (in).

Bit 7:

0 = drive GLOBALCLK out with HCLK
1 = disable.

Bit 8:

0 = CLK_NEG_UP_IN drives CLK_NEG_UP_OUT
1 = HCLK drives CLK_NEG_UP_OUT.

Bit 9:

0 = CLK_NEG_DN_IN drives CLK_NEG_DN_OUT
1 = HCLK drives CLK_NEG_DN_OUT.

[3:0]

Read/Write

ZCT

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