3.1.2. Header interconnect switches

There are electronic switches that route some of the header Z signals:

Sideband signals

These header Z (HDRZ) signals can be directly connected between the two tile sites and allow communication between tiles. They do not connect to other logic on the baseboard.

CLCD signals

The CLCD interface logic and connectors are normally connected to the FPGA. The CLCD can, however, be controlled from either of the tile sites. If neither tile is connected to the CLCD output, the HDRZ signals can be connected together to function as sideband signals.

Peripheral signals

The UARTs, GPIO, SSP, MCI, KMIs, and AACI peripherals are normally connected to the FPGA. These peripherals can, however, be controlled from either of the tile sites. If neither tile is connected to the CLCD output, the header Z signals can be connected together to function as sideband signals.

Unlike the CLCD signals, these peripheral signals are always connected to the FPGA. If a tile drives these signals, the FPGA output signals must be tri-stated.

The controls for the electronic switches come from the control multiplexor PLD. A serial interface implemented in both the PLD and the FPGA copies the value of the SYS_IOSEL register value from the FPGA to the PLD.

See Peripheral I/O select, SYS_IOSEL for the software interface to the control signals.

Sideband signals

Table 4.22 lists HDRZ signals that can be directly connected together. These signals are only used for direct communication between tiles and do not connect to other logic on the baseboard.

The function of the signal depends on the tiles present and the nature of any custom design implemented in the tile FPGAs.

Figure 3.7. Header Z routing switches

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CLCDC routing switches

Figure 3.8 shows the routing logic for the CLCD signals. The signals listed in Table 4.22 control the CLCD signal routing. These switches can be used when a tile (typically a Logic Tile in tile site 2) implements the Color LCD Controller (CLCDC). If a tile is not used as the CLCDC, the header Z signals can be interconnected to enable direct communication between the two tiles.

Figure 3.8. HDRZ switches for CLCDC

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Note

Because the signals are spread over four banks, all four banks must be switched if a tile implements the CLCDC. The register values must be either b01010101 or b10101010. In addition to setting the control signals for the tile routing, signal SWBANKCTL0 must also be set in order to connect the PERIPH[31:0] signals to the CLCD interface logic and connectors.

Peripheral switches

Figure 3.9 shows the peripherals that can be controlled from either of the tile sites. If neither tile is connected to peripherals, the corresponding header Z signals can be connected together to function as sideband signals. See Table 4.22 for details of the mapping between the bits in the SYS_IOSEL register and the switch state.

Some control signals select the source for a single peripheral, for example nENTx_4 for UART0. Other signals select several peripherals at once, for example nENTx_5 for both UART1 and UART2.

Caution

Unlike the CLCDC signals, these peripheral signals are always connected to the FPGA. If a tile drives these signals, logic inside the standard FPGA image monitors these signals and disables the FPGA outputs if a tile drives the signal. If you create a custom image, ensure that the FPGA output signals are tri-stated.

Figure 3.9. HDRZ switches for peripherals

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