3.11.1. About the SMSC LAN9118

The SMCS LAN9118 is a fast Ethernet controller that incorporates a Media ACcess (MAC) Layer, a PHYsical (PHY) layer, and an 8KB dynamically configurable transmit and receive FIFO.

The controller supports dual-speed 100Mbps or 10Mbps and auto configuration. When auto configuration is enabled, the chip is automatically configured for network speed and for full or half-duplex operation.

The controller uses a local VL-Bus host interface that is mapped onto the static memory bus by the configuration PLD. The FPGA generates the appropriate access control signals for the host side of the Ethernet controller.

The LAN9118 is a little-endian device. The default configuration for the system bus is also little-endian. If you configure the system bus for big-endian operation you must perform half-word and byte swapping in software.

A serial EEPROM provides the following parameters to the LAN9118 at reset:

When the baseboard is manufactured, an ARM value for the Ethernet MAC address and the register base address are loaded into the EEPROM. The register base address is 0. A unique MAC address is programmed at manufacture, but the address can be reprogrammed if required. Reprogramming of the EEPROM is done through Bank 1 (general and control registers).


It is possible that application software corrupts the EEPROM contents by writing into the MAC address registers. The fix_EEPROM utility on the CD (and available as a download from the ARM website) can repair the corrupted EEPROM by writing a factory default back to the MAC address. The fix_EEPROM utility can also be used to program any Ethernet MAC address to the baseboard.

Copyright © 2005-2011 ARM Limited. All rights reserved.ARM DUI 0411D