4.19. Synchronous Serial Port, SSP

The PL022 PrimeCell Synchronous Serial Port (SSP) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.

Table 4.69. SSP implementation

Location FPGA
Memory base address0x1000D000
Interrupt 11

9 for transmit

8 for receive

Release versionARM SSP PL022 r1p2
Reference documentationARM PrimeCell Synchronous Serial Port Controller (PL022) Technical Reference Manual (see also Synchronous Serial Port, SSP)

The SSP functions as a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following:

In both master and slave configurations, the PrimeCell SSP performs:

Interrupts are generated to:

The SSP controller can be shared with the following resources:

Copyright © 2005-2011 ARM Limited. All rights reserved.ARM DUI 0411D