4.3.17. DMA peripheral map registers, SYS_DMAPSRx

The DMA map registers, SYS_DMAPSR0 to SYS_DMAPSR3 at 0x10000068 to 0x1000006C, permit the mapping of DMA channels 0, 1, and 2 to three of the external peripherals.

Table 4.19. DMA map registers

Name

Address

Access

Description

SYS_DMAPSR0

0x10000064

Read/Writecontrols mapping to DMA channel 0

SYS_DMAPSR1

0x10000068

Read/Writecontrols mapping to DMA channel 1

SYS_DMAPSR2

0x1000006C

Read/Writecontrols mapping to DMA channel 2

The registers are set to zero by a reset. The DMA mapping is disabled by default. Table 4.20 lists the bit assignments. See Direct Memory Access Controller for more information on the DMA logic.

Figure 4.11. DMA mapping register

DMA mapping register

Table 4.20. SYS_DMAPx, DMA mapping register format

BitAccessDescription
[31:8]-

Reserved. Use read-modify-write to preserve value.

[7]Read/WriteSet to 1 to enable mapping of external peripheral DMA signals to the DMA controller channel.
[6:5]-

Reserved. Use read-modify-write to preserve value.

[4:0]Read/Write

FPGA peripheral mapped to this channel

b00000 = USB A
b00001 = USB B
b00010 = UART3 TX
b00011 = UART3 RX
b00100 = Tile site 1 DMA0
b00101 = Tile site 1 DMA1
b00110 = Tile site 1 DMA2
b00111 = Tile site 2 DMA0
b01000 = Tile site 2 DMA1
b01001 = Tile site 2 DMA2
b01010-b11111 Reserved

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