4.15.2. PCI configuration

This section describes how to configure the PCI controllers on the baseboard and any PCI cards attached to the PCI backplane.

Locating the self-config header table

The slot positions for PCI cards are numbered from 11 to 31. The numbering is based on the address bit that is connected to the IDSEL line. The base address for the PCI configuration header is determined as follows:

0x60000000 + ((slot position)<<11)

For example, if the baseboard is put into slot C where PCI address bit 29 is connected to the IDSEL signal, then the base address for the baseboard header table is at memory location:

0x60000000 + (29<<11) = 0x6000E800

The self-configuration addresses for the slot A, B, and C in the PCI backplane are listed in Table 4.60.

Table 4.60. PCI backplane configuration header addresses (self-config)

SlotAddress connected to IDSELConfiguration header memory
C 29 0x6000E800-0x6000E83F
B300x6000F000-0x6000F03F
A310x6000F800-0x6000F83F

The base address for normal configuration is 0x61000000. The normal configuration addresses for the slot A, B, and C in the PCI backplane are listed in Table 4.60.

Table 4.61. PCI backplane configuration header addresses (normal configuration)

SlotAddress connected to IDSELConfiguration header memory
C 29 0x6100E800-0x6100E83F
B300x6100F000-0x6100F03F
A310x6100F800-0x6100F83F

The contents of the PCI configuration header is listed in Table 4.62. The default values are those of the baseboard.

Table 4.62. PCI configuration space header

Address offsetConfiguration word functionDefault value
+0x00

Device ID Vendor ID

0x030010EE

+0x04

Status Command

0x02200000

+0x08

Class Code Rev ID

0x0B400000

+0x0C

BIST (Reserved in baseboard) Header Type Lat. timer Line Size (Reserved in baseboard)

0x00000000

+0x10Base Address Register 0 (PCI memory space)0x00000001
+0x14Base Address Register 1 (PCI memory space)0x00000008
+0x18Base Address Register 2 (PCI I/O space)0x00000008
+0x1CBase Address Register 3 (reserved in baseboard)-
+0x20Base Address Register 4 (reserved in baseboard)-
+0x24Base Address Register 5 (reserved in baseboard)-
+0x28Cardbus CIS Pointer (reserved in baseboard)-
+0x2C

Subsystem ID Subsystem Vendor ID

0x00000000

+0x30Expansion ROM Base Address (Reserved in baseboard)-
+0x34

Unused (Reserved in baseboard) CapPtr

0x00000000

+0x38(Reserved in baseboard)-
+0x3C

Max_Lat Min_Gnt Interrupt Pin Interrupt line

0x000001FF


The PCI backplane uses the top 3 bits of PCI address to determine whether that slot should respond to configuration cycles. When the baseboard generates PCI configuration cycles by accessing the 0x60000000 or 0x61000000 region, the only one of the PCI cards responds.

See the PCI v2.2 specification for more detail on the configuration space header.

Configuring the PCI interface

To configure a PCI card in the expansion bus, first find the memory location that maps the baseboard into the system:

  1. Scan addresses 0x60000000 + (n<<11) to locate the PCI slot holding the baseboard. The slot range for n is 11 to 31. If you are using the horizontal slot on the PCI expansion backplane, n is 29.

  2. Write the value of n that indicates the slot position into the PCI_SELFID register.

  3. Set bit 2 of the Command/Status Register (at offset +0x04) to enable the baseboard to be initiator on the system. This enables initiator transfers.

  4. Because the PCI_SELFID register now holds the slot number for the baseboard, scanning the normal configuration space at 0x61000000 reveals all PCI cards in the backplane.

    Perform normal configuration cycles on other slot positions to see what else is on the bus. Instead of the self config area at 0x61000000, use memory locations in Config area 0x61000000 + (n<<11), where n is 11 to 31. That is, scan:

    0x61005800, 0x61006000, 0x61006800, and so on to 0x6100F800.

  5. The accesses return 0xFFFFFFFF if the slot is empty, or the device and vendor id for card present. (For the baseboard, the device/vendor id is 0x030010EE.)

    If a card is present, read the base address registers to determine how much and what type of memory is required by each of target boards found in the system.

  6. Write to the base address registers in the header table to setup the PCI memory map and tell each target the PCI memory addresses they should respond to (see Table 4.62).

  7. Set the PCI control registers at 0x10001000 appropriately so an access to one of the three memory regions causes a PCI access to the correct PCI memory location.

Note

An example of PCI scanning and configuration is provided as an example on the CD.

Limitations of the PCI interface

The following limitations apply to the PCI interface present on the baseboard:

  • The interface is 32-bit only (no 64-bit regions).

  • 0-bit, 24-bit and unaligned 16-bit transfers are not supported.

  • The PCI interface is usable with both 3.3V and 5V systems.

  • The initiator creates only single reads and writes. This is quite inefficient and results in low performance. It does, however, simplify the logic in the FPGA and allows 66MHz performance.

  • The target issues a retry response for reads until the data is ready.

  • The target issues a retry response for reads or writes when the fifo is full (target has a 512 deep FIFO, initiator fifo is 16 deep)

  • If another master accesses the baseboard and it responds with 'retry' or 'disconnect without data', then this access must repeated before any other master accesses to the baseboard.

  • The baseboard breaks up burst transfers. It typically completes the first cycle and then responds with 'disconnect without data'. The initiator must then retry with the address that responded with the disconnect.

  • Only three out of five configuration base registers are usable.

  • Cardbus CIS Pointer and Expansion ROM configuration registers are not implemented.

  • There is no support for BIST.

  • The EB cannot generate an interrupt to the PCI bus.

    Note

    This is a departure from the PCI bus specification.

  • The target will only respond to some of sixteen PCI bus commands, and initiator only creates six of the cycle types (see Table 4.63).

Table 4.63. PCI bus commands supported

Command codeNameSupported on targetSupported on initiator
b0000Interrupt AcknowledgeIgnoredNot available
b0001Special CycleIgnoredNot available
b0010I/O readYesYes
b0011I/O writeYesYes
b0100ReservedIgnoredNot available
b0101ReservedIgnoredNot available
b0110Memory ReadYesYes
b0111Memory WriteYesYes
b1000ReservedIgnoredNot available
b1001ReservedIgnoredNot available
b1010Configuration ReadYesYes
b1011Configuration WriteYesYes
b1100Memory Read MultipleYesNot available
b1101Dual Address CycleIgnoredNot available
b1110Memory Read LineYesNot available
b1111Memory Write InvalidateYesNot available

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