4.2.1. Remapping of boot memory

On reset, the processor in the Core Tile begins executing code at address 0x0. This address is normally volatile DRAM. Remapping enables non-volatile static memory to be decoded for accesses to low memory. Remapping of non-volatile memory to the boot region at 0x00000000-0x03FFFFFF is done by the boot select switches, if the REMAP signal inside the FPGA is HIGH, as listed in Table 4.3.

Table 4.3. Boot memory

Switch S8[4:1]Chip selectMemory Range Comment
0000nNOR_CS1 (nSTATICCS0)0x40000000- 0x43FFFFFFNOR flash remapped to 0x0.
0001Reserved (nSTATICCS1)0x44000000- 0x47FFFFFFReserved.
0010nSRAM_CS (nSTATICCS2)0x48000000- 0x4BFFFFFFSRAM remapped to 0x0. The SRAM contents are volatile and are not valid after a power cycle. The contents are valid, however, after the reset switch is pressed.
0011Reserved (nSTATICCS3)0x4C000000- 0x4FFFFFFFReserved.
0100nSTATICCS40x50000000- 0x53FFFFFFPISMO CS1 remapped to 0x0.
0101nSTATICCS50x54000000- 0x57FFFFFFPISMO CS2 remapped to 0x0.
0110nSTATICCS60x58000000- 0x5BFFFFFFPISMO CS3 remapped to 0x0.
0111nSTATICCS70x5C000000- 0x5FFFFFFFPISMO CS0 remapped to 0x0 (this signal is output from the FPGA as nEXP_CS).
1xxxExternal master0x00000000- 0x0FFFFFFF

All accesses are placed on the AXI or AHB master bus. These go to a slave fitted on tile site 2.


Removing boot remapping and enabling DRAM at 0x0

The processor in the Core Tile begins executing at 0x0 after a reset. But because memory mapping is active at reset, the remapping logic causes boot instructions to be fetched from non-volatile static memory. The System Controller SYSCTRL register controls memory remapping. See System Controller.

Note

Refer to the code examples supplied on the CD for an example of boot source code.

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