4.20. Static Memory Controller, SMC

The PrimeCell Static Memory Controller (SSMC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.

Table 4.70. SSMC implementation

PropertyValue
Location FPGA
Memory base address0x10080000
Interrupt NA
DMANA
Release version

ARM SSMC r0p3

Reference documentationARM PrimeCell Static Memory Controller (PL093) Technical Reference Manual, Configuration and initialization

The following key parameters are programmable for each SSMC memory bank:

For information on default values for the memory controllers, see Memory characteristics .

Note

To enable write access to the NOR flash (static chip select 0), set bit 0 of SYS_FLASH to HIGH. The default at power-on reset is LOW.

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