4.3.12. CLCD Control Register, SYS_CLCD

The SYS_CLCD register at 0x10000050 controls LCD power and multiplexing and controls the interface to the touchscreen as listed in Table 4.15. See also LCD power control.

Note

These signals are always driven to the adapter board from the FPGA, even if the CLCD signals come from HDRZ I/O.

Figure 4.8. SYS_CLCD

SYS_CLCD

Table 4.15. SYS_CLCD register

BitsAccessDescription
[31:14]-

Reserved. Use read-modify-write to preserve value.

[13]-Reserved (touchscreen data available on PB926)
[12:8]Read-only

CLCDID[4:0], returns the setting of the ID links on the CLCD adaptor board

Value Display 
0     320x240
1     640x480
2     220x176
3-31  Reserved
[7]Read/WriteSSP expansion chip select. If HIGH, the chip select (SSPnCS) on the SSP expansion connector is active. SSPCS is inverted to SSPnCS at the FPGA pin. See Synchronous Serial Port, SSP.
[6]Read/WriteTouchscreen enable (TSnSS) to controller on CLCD adaptor board
[5]Read/WriteVDDNEGSWITCH[a], enable NEG voltage on the CLCD adaptor board
[4]Read/WritePWR3V5VSWITCHa, enable FIXED voltage on the CLCD adaptor board
[3]Read/WriteVDDPOSSWITCHa, enable POS voltage on the CLCD adaptor board
[2]Read/WriteLCDIOONa, enable the RGB signal buffers on CLCD adaptor board
[1:0] -Reserved (LCD mode)

[a] The voltage control selection in the SYS_CLCD register might be overridden by links on the CLCD adaptor board.


Copyright © 2005-2011 ARM Limited. All rights reserved.ARM DUI 0411D
Non-Confidential