4.8. Direct Memory Access Controller

The PL081 PrimeCell Direct Memory Access Controller (DMAC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.

Table 4.39. DMAC implementation

PropertyValue
Location

FPGA

Note

Some builds do not include the DMA controller. Refer to the Application Note for your product configuration for more details.

Memory base address

0x10030000 for DMAC

0x10000064 for DMA mapping register SYS_DMAPSR0

0x10000068 for DMA mapping register SYS_DMAPSR1

0x1000006C for DMA mapping register SYS_DMAPSR2

Interrupt 24
DMANA
Release versionARM DMAC PL081 r1p2
Reference documentationARM PrimeCell DMA (PL081) Technical Reference Manual (see also DMA)

Sixteen peripheral DMA interfaces are provided by the PrimeCell DMAC, of which twelve are used by the FPGA peripherals (UART0-3, SCI, and SSP) and three are made available for devices in the Logic Tiles.

Note

The DMA controller cannot typically access the Tightly Coupled Memory in the processor on the Core Tile.

The DMA controller is designed to work in two modes:

DMAC flow control

The DMAC is programmed with the amount of data is to be transferred and requires only request signals from the peripheral to show that its buffer is ready for access.

In DMAC flow controller mode each channel requires three signals DMASREQ, DMABREQ and DMACLR.

Peripheral flow control

The DMAC does not know how much data is to be transferred and relies on the peripheral to tell it when the last burst or transfer is to be done.

If the peripheral is the flow controller then five signals are required DMASREQ, DMABREQ, DMACLR, DMALSREQ and DMALBREQ.

Table 4.40 lists the DMA channel allocation.

Table 4.40. DMA channel allocation

PeripheralChannelSignalsSourceNote
UART0 Tx155System FPGADMAC flow control only
UART0 Rx145System FPGADMAC flow control only
UART1 Tx133System FPGADMAC flow control only
UART1 Rx123System FPGADMAC flow control only
UART2 Tx113System FPGADMAC flow control only
UART2 Rx103System FPGADMAC flow control only
SSP0 Tx93System FPGADMAC flow control only
SSP0 Rx83System FPGADMAC flow control only
SCI Tx73System FPGADMAC flow control only
SCI Rx63System FPGADMAC flow control only
AACI Tx53System FPGADMAC flow control only
AACI Rx43System FPGADMAC flow control only
MMCI33System FPGADMAC flow control only
User Defined 225

Tile Sites ,selectable between different sources

Note

The three DMA channels 0, 1, and 2 are connected to the FPGA, but there might be more than three tile peripherals that can use DMA. Three DMA mapping registers control the device that has access to the channels. Table 4.19 lists the register format and possible values.

User Defined 115
User Defined 005

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