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The PL081 PrimeCell Direct Memory Access Controller (DMAC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.
Table 4.39. DMAC implementation
| Property | Value |
|---|---|
| Location | FPGA NoteSome builds do not include the DMA controller. Refer to the Application Note for your product configuration for more details. |
| Memory base address |
|
| Interrupt | 24 |
| DMA | NA |
| Release version | ARM DMAC PL081 r1p2 |
| Reference documentation | ARM PrimeCell DMA (PL081) Technical Reference Manual (see also DMA) |
Sixteen peripheral DMA interfaces are provided by the PrimeCell DMAC, of which twelve are used by the FPGA peripherals (UART0-3, SCI, and SSP) and three are made available for devices in the Logic Tiles.
The DMA controller cannot typically access the Tightly Coupled Memory in the processor on the Core Tile.
The DMA controller is designed to work in two modes:
The DMAC is programmed with the amount of data is to be transferred and requires only request signals from the peripheral to show that its buffer is ready for access.
In DMAC flow controller mode each channel requires three signals DMASREQ, DMABREQ and DMACLR.
The DMAC does not know how much data is to be transferred and relies on the peripheral to tell it when the last burst or transfer is to be done.
If the peripheral is the flow controller then five signals are required DMASREQ, DMABREQ, DMACLR, DMALSREQ and DMALBREQ.
Table 4.40 lists the DMA channel allocation.
Table 4.40. DMA channel allocation
| Peripheral | Channel | Signals | Source | Note |
|---|---|---|---|---|
| UART0 Tx | 15 | 5 | System FPGA | DMAC flow control only |
| UART0 Rx | 14 | 5 | System FPGA | DMAC flow control only |
| UART1 Tx | 13 | 3 | System FPGA | DMAC flow control only |
| UART1 Rx | 12 | 3 | System FPGA | DMAC flow control only |
| UART2 Tx | 11 | 3 | System FPGA | DMAC flow control only |
| UART2 Rx | 10 | 3 | System FPGA | DMAC flow control only |
| SSP0 Tx | 9 | 3 | System FPGA | DMAC flow control only |
| SSP0 Rx | 8 | 3 | System FPGA | DMAC flow control only |
| SCI Tx | 7 | 3 | System FPGA | DMAC flow control only |
| SCI Rx | 6 | 3 | System FPGA | DMAC flow control only |
| AACI Tx | 5 | 3 | System FPGA | DMAC flow control only |
| AACI Rx | 4 | 3 | System FPGA | DMAC flow control only |
| MMCI | 3 | 3 | System FPGA | DMAC flow control only |
| User Defined 2 | 2 | 5 | Tile Sites ,selectable between different sources NoteThe three DMA channels 0, 1, and 2 are connected to the FPGA, but there might be more than three tile peripherals that can use DMA. Three DMA mapping registers control the device that has access to the channels. Table 4.19 lists the register format and possible values. | |
| User Defined 1 | 1 | 5 | ||
| User Defined 0 | 0 | 5 | ||
| Copyright © 2005-2011 ARM Limited. All rights reserved. | ARM DUI 0411D |
| Non-Confidential | |
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