4.2.2. Memory characteristics

Table 4.4 lists the controller memory banks, chip selects, and memory range. Addresses not listed are decoded by the FPGA or passed onto the external buses.

The static memory controller signal nSTATICCS3 and the SMADDR signals are decoded by the configuration PLD to generate nCFGFLASH_CS, ETHnDATACS, and USB_nCS.

Table 4.4. Memory chip selects and address range

BankSignalAddress rangeDevice
DMC bank 4nDDRnCS0

0x00000000-0x0FFFFFFF (0x70000000-0x7FFFFFFF)

DRAM (DRAM mirror)
SMC bank 0nNOR_CS10x40000000-0x43FFFFFFNOR flash
SMC bank 1nNOR_CS20x44000000-0x47FFFFFFNOR flash
SMC bank 2nSRAM_CS0x48000000-0x4BFFFFFFSRAM
SMC bank 3 (additional decoding done by configuration PLD)nCFGFLASH_CS0x4C000000-0x4DFFFFFFConfiguration flash
SMC bank 7



PISMO expansion memory (nCS0)

SMC bank 4nSTATICCS40x50000000-0x53FFFFFFPISMO expansion memory (nCS1)
SMC bank 5nSTATICCS50x54000000-0x57FFFFFFPISMO expansion memory (nCS2)
SMC bank 6nSTATICCS60x58000000-0x5BFFFFFFPISMO expansion memory (nCS3)
-nSTATICCS7-PISMO expansion memory (this signal is tied HIGH inside the FPGA).

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