3.3.2. Reset signals

Table 3.4 describes signals related to reset and configuration. A reset controller implemented in the FPGA monitors the reset sources and generates the appropriate reset signals.

Note

In addition to the hardware reset signals, the system can also be reset from the Watchdog controller.

Table 3.4. Reset and configuration signals

Name

Function

AACIRESET

System reset to audio CODEC.
nBOARDPOR

This signal resets the configuration PLD and configuration flash.

This signal is also used to generate the nTRST pulse at power on.

C_nSRST

JTAG open-collector reset signal to or from the tile. This signal is part of the configuration JTAG chain.

C_nTRST

JTAG open-collector TRST signal to the configuration JTAG chain in the tile. This signal is part of the configuration JTAG chain.

nDOCBUSY

Reserved, this signal is not present on HBI 140 Rev D. (Disk-on-Chip is not available).

nDOCRESET

Reserved, this signal is not present on HBI 140 Rev D. (Disk-on-Chip is not available).

D_nSRST

JTAG open-collector reset request signal to or from the tile. This signal is part of the debug JTAG chain.

A device in the FPGA (the watchdog, for example) can generate a system level reset by pulling the nSRST signal LOW. This will cause the nSYSRST signal to pulse LOW and reset the system. The pulse does not generate a power on reset.

Another example of a reset condition would be the DLLs in the FPGAs losing lock due to a frequency change. Pulling nSRST signal low allows the DLLs to relock. After lock is established, nSRST is released and nSYSRST goes HIGH and the system exits reset.

D_nTRST

JTAG open-collector TRST signal to the debug JTAG chain in the tile. This signal is part of the debug JTAG chain.

ETHRESET

System reset to Ethernet controller (active HIGH).

FPGA_nPROG

The FPGA_nPROG signal forces all FPGAs in the system to reconfigure. This signal enables the FPGAs to be reconfigured without powering-down the system.

LOCAL_DONE

This signal goes HIGH when the baseboard FPGA has finished configuring. GLOBAL_DONE is LOW until this signal goes HIGH.

GLOBAL_DONE

This is an open-collector configuration signal that goes HIGH when all FPGAs have finished configuring. The system is held in reset until this signal goes HIGH.

nPBFPGACONFIG

This signal is generated from the FPGA CONFIG push button and causes a total reconfiguration of the system.

nPBRESET

Push-button reset signal to the FPGA. The signal is generated by pressing the reset button.

P_nRST

System reset from PCI backplane.

PLDRESETn (on Core Tiles)

Reset signals to the configuration PLD located on the Core Tile. Baseboard FPGA signals T1Z229 and T2Z229.

PLDD[1:0] (on Core Tiles)

Data signals to the configuration PLD located on the Core Tile. Baseboard FPGA signals T1Z[228:227] and T2Z[228:227].

PLDCLK (on Core Tiles)

Clock signals to the configuration PLD located on the Core Tile. Baseboard FPGA signals T1Z230 and T2Z230.

P_nTRST

JTAG TRST signal from PCI backplane.

Note

There is a separate JTAG connector and an independent scan chain on the PCI backplane. The JTAG chain on the baseboard does not normally extend to the PCI expansion backplane. There is a separate JTAG connector on the PCI backplane for configuring devices on the backplane and on installed PCI cards. There are also links that can be fitted to the baseboard that connects the two JTAG chains together, but these links are normally only fitted for manufacturing tests.

nRESET

Boot memory remapping signal internal to the FPGA.

nSRST

nSRST is an active LOW open-collector signal that can be driven by the JTAG equipment to generate a nSYSRST system reset request. Some JTAG equipment senses this line to determine when you have reset a board.

This is also used in configuration mode to control the initialization of the FPGA.

Note

nSRST splits into D_nSRST and C_nSRST to provide separate debug and configuration signals on the tile connector HDRZ.

A Logic Tile can generate a reset by pulling this open-collector signal LOW.

nSYSPOR

Power-on reset signal that initializes the reset level state machine after GLOBAL_DONE goes HIGH. This signal is also fed to the tile headers.

nSYSRST

System reset to the Logic Tile headers.

nTRST

Open-collector TAP controller reset, the board drives this signal with nBOARDPOR.

Note

nTRST splits into D_nTRST, and C_nTRST to provide separate debug and configuration signals on HDRZ of the tile.

USBnRESET

System reset to USB controller.

USBWAKEUP

Signal to USB controller to re-initialize.

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