3.5. Memory controllers

The baseboard has two memory controllers implemented in the FPGA:

SMC

The Static Memory Controller (SMC) manages the SRAM, flash, PISMO memory expansion board, Ethernet and USB controllers. See also Static Memory Controller, SMC.

DMC

The Dynamic Memory Controller (DMC) manages the DDR SDRAM mounted on the baseboard. See also Dynamic Memory Controller, DMC.

The static memory controller drives the devices listed in Table 3.5.

Table 3.5. Devices on the static memory bus

DeviceChip selectAddressDescription
NOR flashCS00x4000000064MB of NOR flash
NOR flashCS10x4400000064MB of NOR flash
SRAMCS20x480000002MB of SRAM
Configuration flashCS30x4C0000008MB of configuration flash. This flash holds the image for the FPGA. It must not be used by application code.
EthernetCS30x4E000000The Ethernet controller is mapped into this 16MB space
USBCS30x4F000000The USB controller is mapped into this 16MB space
PISMOCS[7:4]0x50000000

The PISMO memory expansion connector has four chip selects that select four 64MB regions:

nEXPCS 0x5C000000 (PISMO CS0) 
CS4 0x50000000 (PISMO CS1) 
CS5 0x54000000 (PISMO CS2) 
CS6 0x58000000 (PISMO CS3) 

(FPGA CS7, PISMO CS4, is permanently disabled in the FPGA) See Appendix E PISMO Memory Expansion Boards for more details of the PISMO memory expansion cards.


Note

The configuration PLD uses the address bus and the CS[3] signal to generate the device chip selects for the Ethernet controller, the USB controller, and the FPGA configuration flash memory. The FPGA reroutes the static chip selects at power-on-reset to place one of the static devices at address 0x0 as described in Reset logic.

Figure 3.18 shows the memory devices on the static memory bus.

Figure 3.18. Static memory devices

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Figure 3.18 shows the Ethernet controller IC on the static memory bus. For more details on the Ethernet controller, see Ethernet interface, Ethernet, and Ethernet interface.

Figure 3.19. Ethernet device on static memory bus

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Figure 3.18 shows the USB controller IC on the static memory bus. For more details on the USB controller, see USB interface, USB interface, and USB interface.

Figure 3.20. USB device on static memory bus

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The DMC bus is connected to 256MB of DDR SDRAM as shown in Figure 3.21. Series and termination resistors suppress reflections and noise on the control and data lines. The SDRAM is addressed from 0x70000000-0x7FFFFFFF. If REMAPSTAT is HIGH, the memory is also aliased at 0x0-0x0FFFFFFF.

Figure 3.21. Dynamic memory bus

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