3.10. DMA

A PrimeCell DMA controller might be implemented in the FPGA. (Some application notes describe builds that remove the DMA controller in order to increase performance. Refer to the application note that covers your configuration for more details.)

DMA requests from tile sites use DMA channels 0-2. Peripherals in the FPGA use DMA channels 6-15.

DMA control signals for channels 0-2 are passed to the DMA mapping multiplexors in the FPGA. Figure 3.28 shows the DMA architecture.

See also Direct Memory Access Controller.

Note

The DMA control signals have pull-up or pull-down resistors as appropriate. It is not necessary therefore to drive unused signals.

The DMA control signals for external devices are listed in Table 3.11.

Note

Some FPGA peripherals do not use all of the DMA control signals. The USB controller, for example, uses only the DMACSREQ and DMACCLR signals.

Table 3.11. DMA signals for external devices

SignalDescription
DMACBREQ[5:0]Burst request inputs to DMAC for channels 5 to 0.
DMACLBREQ[5:0]Last burst request inputs to DMAC for channels 5 to 0.
DMACSREQ[5:0]Single request inputs to DMAC for channels 5 to 0.
DMACLSREQ[5:0]Last single request inputs to DMAC for channels 5 to 0.
DMACCLR[5:0]Clear outputs from DMAC. These signals acknowledge the request from the corresponding DMASREQ or DMABREQ signals.
DMACTC[5:0]Terminal count outputs from DMAC

Figure 3.28. DMA channels

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