3.17. Two-wire serial bus interface

The FPGA implements a two-wire serial bus interface that is used to identify the memory expansion modules and read and set the time-of-year clock.

Each device on the serial bus has its own slave address. The unique address for each slave on the serial bus is shown in Table 3.15.

Table 3.15. Serial bus addresses

Slave address (7-bit)Slave device
b1010000Reserved
b1010001Static memory module
b1101000Time-of-year clock

The block diagram of the interface is shown in Figure 3.35. See Two-wire serial bus interface for more information on the programming interface.

Figure 3.35. Serial bus block diagram

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Table 3.16 lists the two-wire serial bus signals.

Table 3.16. Two-wire serial bus signals

SignalDescription
SBSCLOpen-collector clock. This clock is driven by the FPGA, but can be held LOW by an external device if it is not ready to receive or transmit data
SBSDAOpen-collector data signal.

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