3.6.2. Peripheral clocks

The following peripherals are present on the baseboard:


The Audio CODEC has a dedicated crystal oscillator. The reference clock from the CODEC is connected to the AACI in the FPGA.


The DMC uses OSCCLK1 for internal timing and to generate the external dynamic memory clocks.


The Ethernet controller has a 25MHz dedicated crystal oscillator for timing the Ethernet bus.


The CLCD controller uses OSC4 as the reference clock for video output.


The MCI uses REFCLK24MHZ for internal and external timing.


The two KMIs use REFCLK24MHZ for internal timing and the generation of the KMI external clocks.


A PCICLK is derived from the 33MHz or 66MHz reference oscillator on the PCI backplane. The PCI clock is connected to the PCI controller in the FPGA to synchronize accesses with the PCI bus. See Peripheral clocks and PCI interface. A signal defined in the FPGA image selects between 33MHz and 66MHz by outputting the P_66EN signal to the backplane. The default is 66MHz.


There is an on board real-time clock module clocked by a dedicated 32.768kHz crystal oscillator. The RTC module outputs full BCD time data to the FPGA via an I2C serial interface.


The SSP uses REFCLK24MHZ for internal and external timing.


The SCI uses REFCLK24MHZ for internal and external timing.


The SMC uses OSCCLK0 for internal timing and to generate the external static memory clocks.


The four timers are clocked with a 35MHz signal and the clock enable signal is selected by the System Controller. The clock enable signal can be configured as permanently high or pulsed. The System Controller has a 1MHz and a 32.768kHz clock. The timer can be configured to run at 35MHz, 1MHz, or 32.768kHz.

Two-wire serial bus

The custom serial bus uses the 24MHz reference for internal timing and to SCL clocks for communication with the expansion memory board and the external time-of-year clock.


The four UARTS use REFCLK24MHZ for internal timing and baud rate generation.


A 12MHz oscillator provides the reference frequency for the external USB controller.


The watchdog timer is clocked with a 1MHz signal derived from REFCLK24MHZ.

Table 3.7 lists the memory and peripheral clocks on the baseboard. For more detail on the clocking system, see the files in the Schematics directory of the CD supplied with the baseboard.

Table 3.7. baseboard clocks and clock control signals

Clock signalFrequencyDescriptionSource
AACIBITCLK12.288MHzThis is the synchronization clock from the audio CODEC. The clock is an input to the AACI PrimeCell.Crystal oscillator
CLCDCLKEXT6-50MHzThe clock for PL110 CLCD Controller in the FPGA is typically derived from OSC4.ICS307 OSC4
ETHLCLKStatic memory clock ETHLCLK is used to synchronize data transfers between the external Ethernet controller and the FPGA. (The Ethernet controller uses a separate 25MHz crystal for clocking signals to and from the Ethernet connector.) 24MHz reference and 25MHz oscillator


24MHzREFCLK24MHZ is generated from OSC0 and the 24MHz crystal. The clock is used as a reference for the timers, USB, Ethernet, MCI, KMI, SSP, SCI, the timer modules, and the watchdog timer. Buffered versions of the reference are REFCLK24MHZ2P, REFCLK24MHZ2F, and REFCLK24MHZ2J. ICS307 OSC0 reference out


12MHzREFCLK12MHZ is generated from OSC4 and the 24MHz reference output from OSC0. ICS307 OSC4 reference out
SCIREFCLKEXT24MHzThe clock for PL131 SCI in the FPGA can be derived from this input. This is a buffered version of REFCLK24MHZ.24MHz reference
SMCLK[2:0]and SMFBCLK-The static memory clocks from the SMC in the FPGA. SMFBCLK is a buffered version of SMCLK2 that is fed back to the SMC to indicate the amount of delay present.SMC
DMC_CLK[4:0] and DMCFBCLK-The dynamic memory clocks from the DMC in the FPGA. DMCFBCLK is a buffered version of DMC_CLK4 that is fed back to the DMC to indicate the amount of delay present between the DMC and the memory device.DMC

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