3.1. Tile headers and signal interconnects

The baseboard has two tile sites that enable adding one or more Core Tiles or Logic Tiles. The signals from the tile sites connect to the FPGA and peripherals on the baseboard. There are also interconnections between the two tile sites.


If a tile site is not fitted with a Core Tile, the function of the signals on HDRX and HDRY can be modified by user for any purpose. Such a change would, of course, require a custom design to be implemented in the baseboard FPGA.

Some of the signals on the tile sites use electronic switches to control the routing, see Header interconnect switches.

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