3.6.1. Tile clocks

The baseboard can be expanded by adding Logic Tiles or Core Tiles. Table 3.6 lists the clock signals that are present on both the baseboard FPGA and the attached tile.

Note

Some of the clocks listed in Table 3.6 might not be present on the baseboard. The clocks used by the baseboard depend on the system configuration and the image loaded into the baseboard FPGA. Refer to the application note that covers your combination of baseboard and Core Tile for more details.

JTAG clocks are not listed in Table 3.6, see JTAG signals for details.

See Tile headers and signal interconnects and the manual for your Logic Tile for details on Logic Tile clocks. See the Core Tile User Guide for details of Core Tile clocks.

Table 3.6. Clock signals on tiles

Tile signalDirection (relative to tile)Description
GLOBALCLKInput/output

A global clock shared with all tiles in the stack. Each tile can accept or drive the signal. This signal can be supplied by ICS307 programmable oscillator 0 (OSCCKL0) on the baseboard.

If the baseboard signal nGLOBALCLKEN is HIGH, the baseboard FPGA drives the GLOBALCLK signal to the tile headers.

CLK_NEG_DN, CLK_POS_DN, CLK_OUT_MINUS1, CLK_UP_THRUOutputClock signals from the tile to the baseboard FPGA.
CLK_NEG_UP, CLK_POS_UP, CLK_IN_MINUS1InputClock signals from the baseboard FPGA to the tile.
CLK_OUT_PLUS1, CLK_OUT_PLUS2, CLK_IN_PLUS1, CLK_IN_PLUS2-These Logic Tile clock signals are not used by the Core Tile or the baseboard. They might be used in some Logic Tile designs. Refer to the documentation supplied with the Logic Tile or the application note for your configuration for more details.
PLDCLKInputThe baseboard clock TnZ230 clocks configuration data into (and status data out of) the PLD on the Core Tile.
REFCLKInputA reference clock to the test chip clock-dividers on the attached tile.
HCLKINInput Tn_X32 from the FPGA can be selected as the source of HCLKIN to the test chip on the Core Tile.
HCLKOUTOutputHCLK from the test chip on the Core Tile.

Figure 3.23. Tile clocks

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