3.6.3. ICS307 programmable clock generators

Five programmable (6-200 MHz) clocks are supplied to the FPGA by the programmable ICS307 clock generators (OSC0-OSC4):

OSCCLK0

This is the reference clock. This is normally used as GLOBALCLK, the external AHB bridge clocks, and the reference for the PLL that generates CPUCLK.

OSC0 uses a 24MHz crystal as its reference. A fixed-frequency 24MHz signal, REFCLK24MHZ, is output from OSC0 and used as a reference signal for:

  • the input for programmable oscillators OSC1-OSC4.

  • the Ethernet controller clock (the Ethernet serial data clock is generated from a 25MHz crystal on the Ethernet controller)

  • the USB controller clock

  • the USB debug controller clock

  • the input to divide-by-24 logic in the FPGA that produces the 1MHz reference clock for the timers.

OSCCLK 1

An alternative reference clock.

OSCCLK2

An alternative reference clock.

OSCCLK3

An alternative reference clock.

OSCCLK4

This the reference for the CLCD controller.

The output frequencies of the ICS307s are controlled by divider values loaded into the serial data input pins on the oscillators. The divider values are defined by the SYS_OSCx registers implemented in the FPGA. The data stream and register format is shown in Figure 3.24. See Oscillator registers, SYS_OSCx for details on the clock control registers.

Figure 3.24. Serial data and SYS_OSCx register format

Serial data and SYS_OSCx register format

Note

Bit 23 is loaded into the shift register first and bit 0 is loaded last. Data is clocked into the ICS307DATA pins of the oscillators on the rising edge of ICS307CLK. One of the ICS307STRB[4:0] signals is pulsed HIGH to latch the serial data into the divider control register.

The serial interface logic is implemented in the standard FPGA design. The only interface to the clock control logic is through the SYS_OSCx registers.

You can calculate the oscillator output frequency from the formula:

where:

VDW

Is the VCO divider word (4 - 511) from SYS_OSCx[8:0]

RDW

Is the reference divider word (1 - 127) from SYS_OSCx[15:9]

DIVIDE

Is the divide ratio (2 to 10) selected from SYS_OSCx[18:16]:

  • b000 selects divide by 10

  • b001 selects divide by 2

  • b010 selects divide by 8

  • b011 selects divide by 4

  • b100 selects divide by 5

  • b101 selects divide by 7

  • b110 selects divide by 3

  • b111 selects divide by 6.

For more information on the ICS clock generator and a frequency calculator, see the ICS web site at www.icst.com. For details of the clock control registers, see Status and system control registers on page 4-18.

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