1.3. Tile interconnections

The two tile sites on the baseboard enable the board to be used with Core Tiles and Logic Tiles. The tiles are stackable and each tile has three connectors on the top and bottom (HDRX, HDRY, and HDRZ).

The bus usage on the tiles and baseboard depend on the type and combination of tiles. HDRX has the master bus signals (AXI, AHB, or ARM7TDMI bus) for both Core Tiles and Logic Tiles. For Logic Tiles, HDRY has the slave bus signals. (See Figure 1.3.)

Some of the I/O devices on the board can be driven by the FPGA or by I/O controllers implemented in a Logic Tile present on tile site 2.

Figure 1.3. Example of bus routing

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For more detail, see Tile headers and signal interconnects.

Note

Some Core Tiles have a second master or slave bus on HDRY. See the documentation for your Core Tile for details of bus usage.

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