4.3. Status and system control registers

The baseboard status and system control registers enable the processor to determine its environment and to control some on-board operations. The registers, listed in Table 4.5, are located from 0x10000000.

The SP810 System Controller manages memory remapping at reset and some clock control functions. See System Controller. See also Reset logic for a description of the reset logic.

Note

All registers are 32 bits wide and do not support byte writes. Write operations must be word-wide and bits marked as reserved must be preserved using read-modify-write.

Table 4.5. Register map for system control registers

NameAddress Access[a]Description
SYS_ID0x10000000Read-onlySystem Identity. See ID Register, SYS_ID.
SYS_SW0x10000004Read-onlyBits [7:0] map to S6 (user switches). See Switch Register, SYS_SW.
SYS_LED0x10000008Read/WriteBits [7:0] map to user LEDs (located next to S6). See LED Register, SYS_LED.
SYS_OSC00x1000000CRead/Write LockableSettings for the ICS307 programmable oscillator chip OSC0. See Oscillator registers, SYS_OSCx.
SYS_OSC10x10000010Read/Write LockableSettings for the ICS307 programmable oscillator chip OSC1.
SYS_OSC20x10000014Read/Write LockableSettings for the ICS307 programmable oscillator chip OSC2.
SYS_OSC30x10000018Read/Write LockableSettings for the ICS307 programmable oscillator chip OSC3.
SYS_OSC40x1000001CRead/Write LockableSettings for the ICS307 programmable oscillator chip OSC4.
SYS_LOCK0x10000020Read/Write Write 0xA05F to unlock. See Lock Register, SYS_LOCK.
SYS_100HZ0x10000024Read-only100Hz counter. See 100Hz Counter, SYS_100HZ.
SYS_CONFIGDATA[2:1] 0x10000028- 0x1000002C-

This region is reserved for registers that are used to configure the clocks and clock dividers on the attached Core Tiles. The location and function of the registers depends on the tile fitted and the FPGA image. See SYS_CONFIGDATAx.

Note

See the application note for the specific combination of baseboard and Core Tile for details of these registers.

SYS_FLAGS0x10000030Read-only

General-purpose flags (reset by any reset). See Flag registers, SYS_FLAGx and SYS_NVFLAGx.

SYS_FLAGSSET0x10000030Write-onlySet bits in general-purpose flags.
SYS_FLAGSCLR0x10000034Write-onlyClear bits in general-purpose flags.
SYS_NVFLAGS0x10000038Read-onlyGeneral-purpose nonvolatile flags (reset only on power up).
SYS_NVFLAGSSET0x10000038Write-onlySet bits in general-purpose nonvolatile flags.
SYS_NVFLAGSCLR0x1000003CWrite-onlyClear bits in general-purpose nonvolatile flags.
SYS_PCICTL0x10000044Read/WriteRead returns a HIGH in bit [0] if a PCI board is present in the expansion backplane. See PCI Control Register, SYS_PCICTL.
SYS_MCI0x10000048Read-only

This was the register for the “card present” and “write enabled” status for the MCI card on the PB926EJ-S development board and is retained for compatibility.

Use GPIO 2 to read the status of these signals on the baseboard.

SYS_FLASH0x1000004CRead/WriteControls write protection of flash devices. See Flash Control Register, SYS_FLASH.
SYS_CLCD0x10000050Read/WriteControls LCD power and multiplexing. See CLCD Control Register, SYS_CLCD.
SYS_CLCDSER0x10000054Read/WriteControl interface to activate the 2.2 inch display on the LCD adaptor. See 2.2 inch LCD Control Register SYS_CLCDSER.
SYS_BOOTCS0x10000058Read-onlyRead register returns the current switch settings of switch S8. See Boot select switch, SYS_BOOTCS.
SYS_24MHZ0x1000005CRead-only32-bit counter clocked at 24MHz. See 24MHz Counter, SYS_24MHZ.
SYS_MISC0x10000060Read-onlyMiscellaneous control flags. See Miscellaneous flags, SYS_MISC.
SYS_DMAPSR00x10000064Read/WriteSelection control for remapping DMA from external peripherals to DMA channel 0. See DMA peripheral map registers, SYS_DMAPSRx.
SYS_DMAPSR10x10000068Read/WriteSelection control for remapping DMA from external peripherals to DMA channel 1.
SYS_DMAPSR20x1000006CRead/WriteSelection control for remapping DMA from external peripherals to DMA channel 2.
SYS_IOSEL0x10000070Read/WriteSelects internal or tile peripheral signals for routing to the peripheral I/O pins. See Peripheral I/O select, SYS_IOSEL.
SYS_PLDCTL[2:1]0x10000074- 0x10000078Read/Write

These registers are to configure the attached Core Tiles (See SYS_PLDCTL[2:1].).

See the application note for the specific combination of baseboard and Core Tile for details of these registers.

Reserved0x1000007C-Reserved.
SYS_BUSID0x10000080Read-onlyResponds with the AXI/AHB bus ID. This enables multiprocessor platforms to determine the primary boot processor. See Bus ID register, SYS_BUSID.
SYS_PROCID[1:0]0x10000084- 0x10000088Read-onlyRead returns a description for the Core Tile present in tile site See Processor ID registers, SYS_PROCID[1:0].
SYS_OSCRESET[4:0]0x1000008C- 0x1000009CRead/Write

Value to load into the SYS_OSC[4:0] registers on a manual reset.

At power-on reset, the SYS_OSCRESET[4:0] registers are loaded with the same default value as used for SYS_OSC[4:0].

Core Tile configuration (SYS_VOLTAGE[7:0])0x100000A0- 0x100000BCRead/Write

This region can contain registers that are used for power management and voltage monitoring of the attached Core Tiles. The location and function of the registers depends on the tile fitted and the FPGA image. See SYS_VOLTAGE[7:0].

See the application note for the specific combination of baseboard and Core Tile for details of these registers.

SYS_TEST_OSC[4:0]0x100000C0- 0x100000D0Read-only32-bit counter clocked from ICS307 oscillators. See Oscillator test registers, SYS_TEST_OSCx.
Reserved0x100000D4- 0x10000FFC-Reserved.

[a] If Access is lockable, the register can only be written if SYS_LOCK is unlocked (see Lock Register, SYS_LOCK).


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