2.1. Setting up the baseboard

The following items are supplied with the baseboard:

To set up the baseboard as a development system:

  1. Set the configuration switches to select the boot memory location and FPGA image. See Setting the configuration switches.

  2. Connect a Core Tile to tile site 1.


    You must ensure that the FPGA image matches the Core Tile you are using. See Connecting a Core Tile.

  3. If you are using a memory expansion board, connect it to the PISMO expansion socket on the baseboard. See Connecting expansion memory and Appendix E PISMO Memory Expansion Boards.

  4. If you are using an external display:

    • For VGA displays, connect the cable from the display to the VGA connector on the baseboard.

    • For Color Liquid Crystal Displays (CLCD), connect the CLCD adaptor board cable to the baseboard. See Appendix C LCD Kits.

  5. Apply power to the baseboard. See Supplying power.


    If you are using the baseboard with the PCI backplane, see Appendix D PCI Backplane and Enclosure. If used with a PCI backplane, the power is supplied from the backplane only.

  6. If you are using Logic Tiles to implement peripherals, mount the tiles in tile site 2. See Connecting a Logic Tile.

    If you are using a second Core Tile to implement a multi-processor system, mount the second Core Tile in tile site 2.

  7. Load a new image into the configuration flash on the baseboard. See Loading FPGA and PLD images and FPGA configuration.

    If you are using a Logic Tile, the configuration flash on the Logic Tile must also contain the appropriate image for the Logic Tile FPGA. See FPGA configuration, the relevant application note, and the documentation for your Logic Tile.


    If the wrong images are loaded into the configuration flash on the baseboard and the Logic Tiles, there might be output signal conflicts that result in excessive power consumption or damage to the boards.

  8. If you are using a JTAG debugger, connect it to the JTAG port on the board. See Connecting JTAG debugging equipment.

  9. If you are using a Trace Port Analyzer (TPA), connect the Trace Port interface buffer board to the connector on the Core Tile. See Connecting the Trace Port Analyzer to the baseboard.

  10. Power off and then power the baseboard back on. The power on sequence for the baseboard is:

    • the image selected by the configuration switches is loaded into the FPGA from the configuration flash

    • after FPGA configuration finishes, the GLOBAL_DONE LED is lit.

    • the processor begins executing instructions in memory at address 0x0.


      The memory-remap switches control the remapping of non-volatile memory to respond at address 0x0 at power on. The non-volatile memory typically contains the Boot Monitor or an operating system loader.

  11. If you are using the supplied Boot Monitor software to select and run an application, see Using the baseboard Boot Monitor and platform library.

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