3.3.3. Power-on reset timing

Figure 3.13 shows the power-on reset sequence. A reset controller implemented in the FPGA monitors nSYSPOR and generates the appropriate reset signals.

nBOARDPOR is generated at power-up and distributed to the memory expansion boards and to the FPGA configuration PLD. It also causes the assertion of the nTRST signal and guarantees the embedded ICE macrocell in the processor core is reset.

Note

The release time for GLOBAL_DONE depends on any Logic Tiles in the system. It is held LOW longer if the tiles take longer to configure.

The system can also be reset from the JTAG signal nTRST or from the system reset signal nSRST as shown in Figure 3.14.

Figure 3.13. Power-on reset and configuration timing

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Figure 3.14. JTAG and system reset

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