3.6. Clock architecture

The clock domains for the baseboard are:

FPGA reference clocks and tile clocks

The FPGA contains clock control logic that sets the frequency of the programmable clock generators. See ICS307 programmable clock generators.

The FPGA also controls the routing of clocks to and from the tile expansion connectors. See Tile clocks for details of the clocks available.

Peripheral clocks

The peripherals on the baseboard use dedicated oscillators or one of the programmable oscillator outputs as a reference clock.

See Peripheral clocks for details.

Debug

The JTAG connector supplies the reference JTAG clock TCK. There is also an on-board USB debug port that is driven by the 24MHz reference and a dedicated 6MHz crystal oscillator. See Test, configuration, and debug interfaces.

Note

The clocking selection and control logic in the baseboard FPGA enables you to emulate many different clock systems and operating modes.

The clocks used depend on the type and configuration of tiles added to the baseboard. See the application notes for examples of different combinations of boards.

The clock domains for the baseboard are shown in Figure 3.22.

Figure 3.22. Clock architecture

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