3.23.1. JTAG and USB debug port support

The baseboard supports debugging using embedded or external hardware. The debugging interface can be controlled by:

JTAG hardware

The RealView Debugger and the AXD debugger, for example, use an external interface box, such as RealView ICE or Multi-ICE, to connect to the JTAG connector. The progcards_rvi.exe (or progcards_multiice.exe) utility uses the JTAG interface to load FPGA and PLD images.

USB debug port

The USB debug port is embedded on the baseboard. The progcards_usb.exe utility controls the JTAG signals from the USB port of the PC. The PC and the baseboard are connected by a standard USB cable. The USB debug port is only used for loading FPGA and PLD images and is not available as a general debug port.


ARM Multi-ICE and RealView ICE ground pin 20 of the JTAG connector as shown in Figure 3.43. On the baseboard, pin 20 is connected to a pull-up resistor and the nICEDETECT signal. The USB debug port is automatically disabled if a JTAG emulator is connected and nICEDETECT is LOW. If you are using third-party debugging hardware, ensure that a ground is present on pin 20 of the JTAG connector.

Figure 3.43. External connection to ground for nICEDETECT signal

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The baseboard has two scan chains:


The D_x signals are used for the processor in the Core Tiles and synthesized JTAG TAP controllers in the Logic Tile. This is the normal mode of operation (see JTAG debug (normal) mode).


The C_x signals are used to program the PLDs and to load the FPGA images into configuration memory. This chain is available in configuration mode (see JTAG configuration mode). See also Integrated Logic Analyzer.

JTAG debug (normal) mode

During normal operation and software development, the baseboard operates in debug mode.

The debug mode is selected by default (when the CONFIG link is in the OFF position). In debug mode:

  • The signal nCFGEN is HIGH.

  • The CONFIG LED is OFF on the baseboard (and on each Logic Tile in the stack).

  • A debugger, RealView Debugger for example, controls the scan chain.

  • The PLDs and FPGAs are not visible on the scan chain unless they contain debuggable devices.


    The images supplied with the baseboard route the D_TDO and D_TCK signals through the FPGA. If you load a custom image into the FPGA, ensure that the image also routes the input signals to the output signals to prevent the debug chain from being broken.

  • The JTAG signals are routed through the TAP controller in the Core Tile processor.

  • If Logic Tiles are present and have debuggable devices, the T1_D_x and T2_D_x signals are present in the JTAG scan chain.

    If Logic Tiles are present, but do not have debuggable devices, the Logic Tile FPGA signal D_TDI must be routed to D_TDO and the D_TCK signal must be routed to D_RTCK

  • The FPGAs in the system load their images from configuration flash.

JTAG configuration mode

This mode is selected if the CONFIG switch is in the ON position. In configuration mode:

  • The signal nCFGEN is low.

  • The CONFIG LED is lit on the baseboard (and on each tile in the stack).

  • The JTAG scan path is routed to include configurable devices.

  • A configuration program (one of the progcards utilities for example) controls the scan chain.

  • If one or more Logic Tiles are present, the T1_C_x and T2_C_x signals are part of the JTAG scan chain.

  • All FPGAs and PLDs in the system (including any devices in a Logic Tile) are added into the scan chain.

  • The TAP controller in the Core Tile processor is not visible and is replaced by a Boundary Scan TAP controller that is used for board-level production testing.


    Some versions of the CT7TDMI do not have a boundary scan tap controller and the test chip is bypassed when in configuration mode.

  • This enables the board to be configured or upgraded in the field using JTAG equipment or the onboard USB debug port.

  • The non-volatile PLD devices can be reprogrammed directly by JTAG.

  • The FPGA image is loaded from the configuration flash, however, a new image for the FPGA or the configuration flash can be loaded from the scan chain.

    The FPGAs are volatile. In normal mode, they load their configuration from non-volatile flash memory. In configuration mode, they can be loaded from either JTAG or the configuration flash memory. See FPGA configuration for details of loading a PLD or FPGA image.


    The configuration flash memory does not have a JTAG port, but it can be programmed using JTAG by loading a flash-loader design into the FPGAs and PLDs. The flash-loader can then transfer data from the JTAG programming utility to the configuration flash. This process is managed automatically by the progcards utility.

After configuration you must:

  1. move the config switch to the OFF position

  2. power cycle the development system.

JTAG signals

Table 3.21 provides a description of the JTAG and related signals.


In the description in Table 3.21, the term JTAG equipment refers to any hardware that can drive the JTAG signals to devices in the scan chain. Typically this is RealView ICE, Multi-ICE, or the embedded USB debug logic.

Table 3.21. JTAG related signals





Test data in

(from JTAG equipment)

TDI and TDO connect each component in the scan chain.


Test data out

(to JTAG equipment)

TDO is the return path of the data input signal TDI. The JTAG components are connected in the return path so that the length of track driven by the last component in the chain is kept as short as possible.


Test mode select

(from JTAG equipment)

TMS controls transitions in the TAP controller state machine.


Test clock

(from JTAG equipment)

TCK synchronizes all JTAG transactions. TCK connects to all JTAG components in the scan chain. Series termination resistors are used to reduce reflections and maintain good signal integrity.


Return TCK

(to JTAG equipment)

Some devices sample TCK and delay the time at which a component actually captures data. Using a mechanism called adaptive clocking, the RTCK signal is returned by the core to the JTAG equipment, and the TCK is not advanced until the core has captured the data. In adaptive clocking mode, RealView ICE or Multi-ICE waits for an edge on RTCK before changing TCK. In a multiple device JTAG chain, the RTCK output from a component connects to the TCK input of the next device in the chain.


Configuration enable

nCFGEN is an active LOW signal used to put the boards into configuration mode. In configuration mode all FPGAs and PLDs are connected to the scan chain so that they can be configured by the JTAG equipment. The baseboard JTAG routing PLD is not accessible.


System reset (bidirectional)

nSRST is an active LOW open-collector signal that can be driven by the JTAG equipment to reset the target board. Some JTAG equipment senses this line to determine when a board has been reset by the user.

This is also used in configuration mode to control the initialization pin (nINIT) on the FPGAs.

Though not a JTAG signal, nSRST is described because it can be controlled by JTAG equipment.


Test reset (from JTAG equipment)

This active LOW open-collector signal is used to reset the JTAG port and the associated debug circuitry on the tiles. It is asserted at power-up, and can be driven by the JTAG equipment. This signal is also used in configuration mode to control the programming pin, nPROG, on FPGAs.


Debug request

(from JTAG equipment)

DBGRQ is a request for the processor core to enter the debug state. It is provided for compatibility with third-party JTAG equipment. The processor enters debug state and issues a DBGACK to acknowledge the request.


All FPGAs configured

GLOBAL_DONE is an open-collector signal that indicates when all FPGA configuration is complete. Although this signal is not a JTAG signal, it does affect nSRST. The GLOBAL_DONE signal is routed between all RealView boards.


Return TCK enable

nRTCKEN is an active LOW signal driven by any tile that requires RTCK to be routed back to the JTAG equipment. If nRTCKEN is HIGH, the baseboard drives RTCK LOW. If nRTCKEN is LOW, the baseboard drives the TCK signal back to the JTAG equipment.


To JTAG routing PLD

nTILEDET is LOW if a tile is attached to the tile site. This signal controls routing the JTAG signals for the tile headers.

Figure 3.44. JTAG signal routing

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The JTAG path chosen depends on whether the system is in configuration mode or debug mode. The CONFIG switch controls the nCFGEN signal that is routed through the baseboard and tile connectors. Figure 3.44 and Figure 3.45 shows the JTAG signal routing.


The JTAG routing PLD (not shown in the figures below) connects to both debug and configuration JTAG chains on the FPGA and tiles. The TAP chain selected is determined by the setting of the CONFIG switch.

The JTAG routing PLD is pre-programmed at manufacture and is not part of the JTAG scan chain in either mode.

Figure 3.45. JTAG signal routing in config mode

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Figure 3.46. JTAG signal routing in debug mode

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