3.3. Reset logic

The reset logic initializes attached Logic Tiles and Core Tiles, the FPGA, and external controllers as a result of a reset. The baseboard reset sources are listed in Table 3.3.

Table 3.3. Reset sources

Power applied to boardnBOARD_PORWhen the power is applied (or restored after a power failure), the nBOARD_POR signal is generated.

Reset push button


Resets the system without reloading the FPGA image. The effect on the system is the same as the nBOARD_POR signal going active.

FPGA reload push button


Resets the system and reloads the FPGA images in the baseboard, Core Tiles, and Logic Tiles.


Use the FPGA CONFIG push button to reload the FPGA image without repowering the entire system. The FPGA configuration registers are reloaded with their default values. Pressing FPGA CONFIG also resets the core.

PCI backplaneP_nRSTThere is a reset switch on the PCI backplane. The signal can also be generated by a PCI card installed in the backplane.
Logic TilesnSYSPOR (or D_nSRST)These signals can be generated by custom logic implemented in the Logic Tiles
JTAGnTRSTThe JTAG reset signal can be triggered by an attached JTAG debugging interface device.
Watchdog-If the Watchdog timer is enabled and times out, a reset is generated.

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