4.12.1. Interrupt controller registers

There are two logical banks of register used in the interrupt controllers:

CPU interface

The CPU interface is essentially a slave to each CPU which supports the Generic Interrupt Controller Architecture, and is responsible for holding the interrupt priority mask which is software programmable and for handling preempted interrupts. A pending interrupt is only accepted if its priority is higher than the priority mask and also higher than the priority of the highest priority active interrupt active on that CPU (that is, including those that have been pre-empted).

Distribution

The Interrupt Distributor centralizes all interrupt sources for handling by the Distributor before dispatching the highest priority ones to the interrupt interface appropriate CPU for Priority Masking and Pre-emption handling.

When an interrupt is signalled to the CPU, the CPU responds and the initial interrupt handler reads the number of the interrupt, and as a side-effect of this read, the priority of this interrupt is recorded within the CPU Interface, and that interrupt is now denoted as being active for that CPU within the distributor. Due to the programmability of the priority mask, it is possible for the interrupt to be of a lower priority than the priority mask at the time that the interrupt number is read - in this case, the interrupt number returned is 1023, indicating a spurious interrupt.

When an interrupt is completed by a CPU, the CPU software writes to the CPU Interface in the controller to indicate completion of the interrupt, passing the interrupt number as a final argument. This causes the interrupt to be marked as Inactive for that CPU within the distributor.

Note

The GIC design supports multiple CPUs for each controller. For the standard image shipped in the baseboard however, only one CPU is managed by each controller.

CPU interface registers

The CPU interface registers for the are listed in Table 4.47.

Table 4.47. GIC interface registers

Address offset

Name

Access

Description

0x0000

CPUControl

Read/Write

Control register. Set bit 0 to 1 to enable interrupts to this CPU.

0x0004

Priority

Read/Write

Priority mask register. The CPU interface asserts an interrupt request to CPU if, and only if, the priority of the highest pending interrupt sent by the interrupt distributor is strictly higher than the mask set in Priority mask register.

0x0008

Point

Read/Write

Binary point register. Bits [2:0] determine which bits of the priority register are used to determine pre-emption:

0 Bits[7:1] of the priority are used to determine pre-emption
1 Bits[7:2] of the priority are used to determine pre-emption
2 Bits[7:3] of the priority are used to determine pre-emption
3 Bits[7:4] of the priority are used to determine pre-emption
4 Bits[7:5] of the priority are used to determine pre-emption
5 Bits[7:6] of the priority are used to determine pre-emption
6 Bit[7] of the priority is used to determine pre-emption
7 No pre-emption is performed, but all bits of the priority are used for prioritization

0x000C

Acknowledge

Read-only

Interrupt acknowledge register. Bits [9:0] contain the interrupt identifier.

0x0010

EndInterrupt

Write-only

End of interrupt register. This write-only register is used when the software has finished handling an interrupt. This will reset the interrupt to Inactive for this processor.

0x0014

Running

Read-only

Running priority register. This read-only register contains the priority level of the currently running interrupt on this CPU. When no interrupt is running (that is, acknowledged but reading acknowledge register but not ended by writing to EOI register), priority value read is 0xFF.

0x0018

Highest Pending

Read-only

The Highest Pending Interrupt Register contains the Interrupt ID of the Highest Pending Interrupt that has been selected by the Distributor for this CPU. If no interrupt is pending, the Interrupt ID returned is 1023, Spurious Interrupt.

0x001C-0x00CF

Reserved--

0x00D0-0x00FF

CPU_IF_ID

Read-only

Identification registers

Distribution registers

The distribution registers for the interrupt controllers are listed in Table 4.48.

Table 4.48. GIC distribution registers

Address offset

Name

Access

Description

0x1000

Control

Read/Write

Control register. Set bit 0 to 1 to enable interrupts.

0x1004

Controller type

Read-only

Identifies number of CPUs for this controller and the number of interrupt lines the controller services.

This register must contain the value 0x00000002 (1 CPU and 96 interrupt lines).

0x1008-0x10FC

Reserved--

0x1100

Enable set

Read/Write

Enable set register (interrupts 0-31)

Bit 0 corresponds to interrupt signal 0.

0x1104

Enable set

Read/Write

Enable set register (interrupts 32-63)

0x1108

Enable set

Read/Write

Enable set register (interrupts 64-95)

0x110C-0x117C

Reserved--

0x1180

Clear

Read/Write

Interrupt enable clear register (0-31)

0x1184

Clear

Read/Write

Interrupt enable clear register (32-63)

0x1188

Clear

Read/Write

Interrupt enable clear register (95-64)

0x118C-0x11FC

Reserved--

0x1200

Pending set

Read/Write

Pending set register (0-31)

0x1204

Pending set

Read/Write

Pending set register (32-63)

0x1208

Pending set

Read/Write

Pending set register (95-64)

0x120C-0x127C

Reserved--

0x1280

Pending clear

Read/Write

Pending clear register (0-31)

0x1284

Pending clear

Read/Write

Pending clear register (32-63)

0x1288

Pending clear

Read/Write

Pending clear register (95-64)

0x128C-0x12FC

Reserved--

0x1300

Active

Read-only

Active bit register (0-31). The active register is used to allow the software to know which interrupts are currently active (bit read as 1) on one or more CPUs. They are read-only registers, and writes to these registers are ignored.

0x1304

Active

Read-only

Active bit register(32-63)

0x1308

Active

Read-only

Active bit register (95-64)

0x130C-0x13FC

Reserved--

0x1400-0x143C

Priority

Read/Write

Priority registers (interrupts 0-63)

Eight bits are used to set the priority for each interrupt source. There are therefore four interrupt lines configured for each 32-bit word.

0x1440-0x17FC

Reserved--
0x1800-0x185CCPU TargetsRead/Write

CPU Targets (0-31)

You must only access Bit[0]. At reset this value is set to 0, you must write a 1 to this bit to enable interrupts to pass to the Core Tile. This bit is automatically set to 1 if you are running boot monitor.

0x1860-0x1BFC

Reserved--

0x1C00

Configuration

Read/Write

Configuration registers (0-15). Interrupt configuration registers are used to define what event denotes the assertion of the interrupt. Each interrupt uses two bits:

b00 Active-high, N-N software model
b01 Active-high, 1-N software model
b10 Rising-edge, N-N software model
b11 Rising-edge, 1-N software model

0x1C04

Configuration

Read/Write

Configuration registers (16-31)

0x1C08

Configuration

Read/Write

Configuration registers (32-47)

0x1C0C

Configuration

Read/Write

Configuration registers (48-63)

0x1C10

Configuration

Read/Write

Configuration registers (64-79)

0x1C14

Configuration

Read/Write

Configuration registers (80-95)

0x1C18-0x1EFC

Reserved--

0x1F00

SoftwareWrite-onlySoftware interrupt register. The Software interrupt register is a write-only register that is used to trigger an interrupt to a CPU. Bits [9:0] contain the interrupt ID.

0x1FD0

GICPeriphID

Read-only

Peripheral identification registers

0x1FFC

GICPCellID

Read-only

Identification registers


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