3.2. FPGA

Figure 3.10 shows the architecture of the FPGA on the baseboard.

Figure 3.10. FPGA block diagram

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For more detail on FPGA components, see:

Note

The FPGA buses on the baseboard are shared with the tile site 1 and tile site 2 headers. Use the appropriate FPGA image to ensure that the tiles bus signals match the FPGA signals.

The peripherals and controllers implemented in the baseboard FPGA are in the standard images distributed by ARM Ltd.

The logic shown in Figure 3.10 is for the default image. You can replace some or all of the logic in the FPGA with your own designs, however, the details of how to do this are beyond the scope of this user guide. The CD includes FPGA HDL and signal definition files that can be used as a basis for custom designs.

The PrimeCell peripherals used in the baseboard FPGA are supplied as black-box implementations. The internal design of the peripheral is not configurable or viewable.

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