A.8.1. Expansion connector

The memory expansion board uses a 120-way QSH Samtec connector as shown in Figure A.8. The baseboard uses the corresponding QTH connector. The pinout is listed in Table A.8.

Note

The numbering of pins is for the view facing the connector. Some PISMO boards also have a QTH connector on the top of the memory board to enable stacking.

Table A.7. Samtec part numbers

HeaderPart numberMating height
baseboard (and PISMO board top)QTH-060-01-F-D-A5mm
PISMO board (bottom)QSH-060-01-F-D-A5mm

Figure A.8. Samtec connector

Samtec connector

Table A.8. Memory connector signals

Pin No.Signal Pin No.Signal
1DATA[0] 23V3
3DATA[1] 43V3
5DATA[2] 63V3
7DATA[3] 83V3
9DATA[4] 10VDDIO[a]
11DATA[5] 12VDDIOa
13DATA[6] 14VDDIOa
15DATA[7] 16VDDIOa
17DATA[8] 181V8
19DATA[9] 201V8
21DATA[10] 221V8
23DATA[11] 241V8
25DATA[12] 26nDRQ
27DATA[13] 28Reserved, do not drive
29DATA[14] 30Reserved, do not drive
31DATA[15] 32Reserved, do not drive
33DATA[16] 345V
35DATA[17] 365V
37DATA[18] 385V
39DATA[19] 405V
41DATA[20] 42Reserved, do not drive
43DATA[21] 44Reserved, do not drive
45DATA[22] 46Reserved, do not drive
47DATA[23] 48Reserved, do not drive
49DATA[24] 50Reserved, do not drive
51DATA[25] 52Reserved, do not drive
53DATA[26] 54DEMUX
55DATA[27] 56nSTANDBY
57DATA[28] 58Reserved, do not drive
59DATA[29] 60Reserved, do not drive
61DATA[30] 62SCL, E2PROM serial interface clock (3.3V signal level)
63DATA[31] 64SDA, E2PROM serial interface data (3.3V signal level)
65ADDR[0] 66nRESET
67ADDR[1] 68nPOR, asserted on hardware power cycle
69ADDR[2] 70nWP, flash write protect. Drive HIGH to write to flash.
71ADDR[3] 72nRESET_REQ, Reset signal. Differs from nRESET in that it is not delayed by nWAIT.
73ADDR[4] 74nBUSY, Wait mode input from external memory controller. Pull HIGH if not used.
75ADDR[5] 76nBWAIT, Synchronous burst wait input. This is used by the external device to delay a synchronous burst transfer if LOW. Pull to HIGH if not used.
77ADDR[6] 78Reserved, do not drive
79ADDR[7] 80nCS[4]
81ADDR[8] 82nCS[3]
83ADDR[9] 84nCS[2]
85ADDR[10] 86nCS[1]
87ADDR[11] 88ADDR[29]
89ADDR[12] 90ADDR[28]
91ADDR[13] 92ADDR[27]
93ADDR[14] 94ADDR[26]
95ADDR[15] 96nCS[0]
97ADDR[16] 98nRESET_BUSY, Indicates that memory is not ready to be released from reset. If LOW, this signal holds nRESET active.
99ADDR[17] 100nIRQ
101ADDR[18] 102nWE
103ADDR[19] 104nOE
105ADDR[20] 106nBE[3], Byte Lane Select for bits [31:24]
107ADDR[21] 108nBE[2], Byte Lane Select for bits [23:16]
109ADDR[22] 110nBE[1], Byte Lane Select for bits [15:8]
111ADDR[23] 111nBE[0], Byte Lane Select for bits [7:0]
113ADDR[24] 114WIDTH[0], Indicates bus width for fitted part. Do not route through stackable boards.
115ADDR[25] 116WIDTH[1], Indicates bus width for fitted part. Do not route through stackable boards.
117nLBA, Indicates that the address output is stable during synchronous burst transfers 118CLK[1], a buffered version of SMCLK[1].
119BAA, Burst Address Advance. Used to advance the address count in the memory device 120CLK[0], a buffered version of SMCLK[0].

[a] VDDIO is the data voltage to host. Do not route through on stackable boards


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