3.1.1. Buses

The bus usage on the tiles and baseboard depends on the type and combination of tiles. HDRX has the master bus signals for both Core Tiles and Logic Tiles. For Logic Tiles, HDRY has the slave bus signals.

The signals on the header connectors depend on the bus present:

AXI

For a Logic Tile, HDRX implements the master AXI bus and HDRY implements an AXI slave bus. For a Core Tile, HDRX implements the AXI master bus. A master or slave bus might be implemented on HDRY.

AXI buses have too many signals to fit on HDRX or HDRY. Multiplexors in the Core Tile reduce the number of signals required on the header connectors as shown in Figure 3.2. Table 3.1 lists the timing specifications for the multiplexor. Some AXI signals are extremely time critical and are not passed through the multiplexors.

AHB

For a Logic Tile, HDRX implements a master AHB bus and HDRY implements a AHB slave bus. See Figure 3.1. For a Core Tile, HDRX implements an master bus. A master or slave bus might be implemented on HDRY.

ARM7

HDRX on the tile site connected to the Core Tile implements an ARM7TDMI or ARM7-S bus. For a Logic Tile, HDRX implements an AHB master bus and HDRY implements am AHB slave bus.

The organization is the same as shown for the AHB bus in Figure 3.1, but the control signals and the data bus interconnects on the Core Tile are different. The baseboard FPGA provides an AHB wrapper for the ARM7 bus variants.

Core Tiles with AHB buses have interconnect switches that control the routing of the read and write data buses from the tile header to the processor pins. The baseboard, however, has only one data bus on HDRX so the HWDATA and HRDATA signals are always multiplexed as HDATA. HDRY has enough signals to enable the Logic Tile to use separate HWDATA and HRDATA buses, but the example implementation also uses multiplexed HDATA on HDRY to simplify implementing the interfaces.

Figure 3.1. Example of an AHB bus interface

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The Core Tiles with AXI buses have multiplexors that reduce the number of signals used.

Figure 3.2. Example of a multiplexed AXI bus interface

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Figure 3.3. AXI multiplex timing

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Table 3.1 lists the timing specification, with 50MHz clock assumed, for the AXI multiplexor and demultiplexor. CLKin is the clock driven to the test chip from the board. All I/O timing must be with respect to this clock.

Table 3.1. AXI multiplexor timing

SignalTimeDescription
Toh (min.)0nsOutput hold
Tov (max)2nsOutput valid
Tis (max)2nsInput setup
Tih (max)0nsInput hold
Tmux (max)6nsMultiplexor and board delay

Bus signals on headers

The tile buses support AHB, AXI, custom, and peripheral buses as shown in Table 3.2.

Table 3.2. Bus usage on tile sites

TileHeaderDescription
Core TileHDRX

Master bus.

For Core Tiles that have AHB buses, the HRDATA and HWDATA are tri-state multiplexed onto a single bidirectional HDATA bus.

For Core Tiles that have AXI buses, the signals are time-domain multiplexed to reduce the width of the output and input buses.

HDRY

HDRY is used for control signals for Core Tiles that have AHB buses.

HDRY might implement a second master or a slave for Core Tiles that use multiple AXI buses.

HDRZSideband signals such as I/O signals, JTAG, clocks, and custom interconnection signals. The use of these signals depends on the specific Core Tile.
Logic TileHDRX

Master bus

For AHB, the two read and write data buses are tri-state multiplexed onto a single bidirectional HDATA bus.

For AXI, the output and input buses are each time-domain multiplexed to reduce the bus width.

HDRY

Slave bus

For AHB, the two read and write data buses are tri-state multiplexed onto a single bidirectional HDATA bus.

For AXI, the output and input buses are each time-domain multiplexed to reduce the bus width.

HDRZSideband signals and I/O. The use of these signals depends on the specific Core Tile and the design implemented in the Logic Tile FPGA.

Figure 3.4 shows a basic system consisting of one Core Tile. The FPGA on the baseboard implements interface devices and provides a bus interface to the Core Tile.

Figure 3.4. Core Tile in site 1

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Figure 3.5 shows a system consisting of one Core Tile and a Logic Tile. The FPGA provides a bus interface to the Core Tile.

The peripherals can be implemented either in the FPGA on the Logic Tile or the FPGA on the baseboard, see Header interconnect switches.

Figure 3.5. Core tile in site 1 and Logic Tile in site 2

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Figure 3.6 shows a dual Core Tile system. The FPGA implements interface devices and provides the bus interfaces to the Core Tiles.

Figure 3.6. Dual Core Tile system

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