4.12.2. Interrupt signals

The device interrupts are listed in Table 4.49.

Note

Refer to the application note for your product configuration for details on how interrupts are handled for your system and the interrupts signals present on the connectors.

Table 4.49. Interrupt signals to controllers

BitInterrupt sourceDescription
[95:84]Reserved-
[83]PCI3

Interrupts from PCI expansion bus

Note

The EB cannot generate an interrupt to the PCI bus.

This is a departure from the PCI bus specification.

[82]PCI2
[81]PCI1
[80]PCI0
[79]T2_INT7

Interrupts from tile site 2

[78]T2_INT6
[77]T2_INT5
[76]T2_INT3
[75]T2_INT3
[74]T2_INT2
[73]T2_INT1
[72]T2_INT0
[71]T1_INT7

Interrupts from tile site 1

[70]T1_INT6
[69]T1_INT5
[68]T1_INT3
[67]T1_INT3
[66]T1_INT2
[65]T1_INT1
[64]T1_INT0
[63]TSnKPADIRQ Touch screen pen interrupt
[62]TSnPENIRQTouch screen keypad interrupt
[61]USBInterrupt from USB controller IC
[60]EthernetInterrupt from Ethernet controller IC
[59]PISMOInterrupt from memory expansion board (was also shared with Disk-on-Chip interrupt on Revision C board)
[58]Reserved-
[57]PWRFAILPower failure signal from FPGA
[56]DMACDMA controller
[55]CLCDCLCD display (from adapter board)
[54]LCDCharacter LCD display
[53]KMI1Keyboard/Mouse Interface
[52]KMI0Keyboard/Mouse Interface
[51]AACICODEC controller interrupt
[50]MCIbMultimedia Card Interface interrupt b
[49]MCIaMultimedia Card Interface interrupt a
[48]SCISmart Card interface
[47]UART3UART3
[46]UART2UART2
[45]UART1UART1
[44]UART0UART0
[43]SSPSynchronous serial port
[42]RTCReal time clock
[41]Reserved-
[40]GPIO2GPIO controller (various board I/O signals)
[39]GPIO1GPIO controller
[38]GPIO0GPIO controller
[37]Timer 2 or 3Timers
[36]Timer 0 or 1Timers
[35]COMMTX

Debug communications transmit interrupt.

tile site 1 to GIC1 and 2

tile site 2 to GIC 3 and 4

This interrupt indicates that the communications channel is available for the processor to pass messages to the debugger.

[34]COMMRX

Debug communications receive interrupt.

tile site 1 to GIC 1 and 2

tile site 2 to GIC 3 and 4

This interrupt indicates to the processor that messages are available for the processor to read.

[33]Software interrupt

Software interrupt. Enabling and disabling the software interrupt is done with the Enable Set and Enable Clear Registers. Triggering the interrupt however, is done from the Soft Interrupt Set register.

[32]WatchdogWatchdog timer
[31:16]GICReserved for GIC software interrupts
[15:0]GICSoftware interrupts

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