4.15.1. Control registers

The PCI_IMAPx, PCI_SMAPx, PCI_SELFID, and PCI_FLAGS registers control the operation of the PCI bus and provide status information. The PCI_IMAPx and PCI_SMAPx registers define the address translation values for the PCI I/O, PCI configuration, and PCI memory windows. See Table 4.54.

Table 4.54. PCI controller registers

AddressNameAccessDescription
0x10019000PCI_IMAP0Read/Write

Translate board address to PCI address for accesses 0x63000000-0x63FFFFFF.

0x10019004PCI_IMAP1Read/Write

Translate board address to PCI address for accesses 0x64000000-0x67FFFFFF.

0x10019008PCI_IMAP2Read/Write

Translate board address to PCI address for accesses 0x68000000-0x6FFFFFFF.

0x1001900CPCI_SELFIDRead/WriteSlot location of the baseboard.
0x10019010PCI_FLAGSRead/WriteMaster and target abort flags.
0x10019014PCI_SMAP0Read/Write

Translate PCI base address region 0 to board address.

0x10019018PCI_SMAP1Read/Write

Translate PCI base address region 1 to board address.

0x1001901CPCI_SMAP2Read/Write

Translate PCI base address region 2 to board address.


PCI_IMAPx registers

The PCI_IMAPx registers translate memory address bits for the PCI regions. The number of register bits used in the transformation depend on the memory region size, see Table 4.55. In the example shown in Figure 4.18, the PCI_IMAP2 register contains 0x80000000 and this is used for the six high bits of the PCI address bus. Bits [31:26] are used because a 64MB region is being addressed.

Figure 4.18. Baseboard to PCI mapping

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The map register formats are shown in Figure 4.19 and Table 4.58.

Figure 4.19. PCI_IMAPx register

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Table 4.55. PCI_IMAPx register format

BitsDescription
[31:24]

Contains the value to use for the upper bits of the PCI address for accesses to this region.

Note

Bits that are not used for remapping are ignored and the corresponding bits from the baseboard address are used to complete the PCI address:

  • PCI_IMAP2 uses bits [31:27] to map the 128MB baseboard region to PCI addresses

  • PCI_IMAP1 uses bits [31:26] to map the 64MB baseboard region to PCI addresses

  • PCI_IMAP0 uses bits [31:24] to map the 16MB baseboard region to PCI addresses.

[23:0]

Reserved.


PCI_SELFID register

Writing the slot location of the baseboard into this register enables normal configuration accesses to return information on the baseboard. That is, normal configuration accesses to this slot position are converted automatically into self-configuration accesses.

The register format is shown in Figure 4.20 and Table 4.56.

Figure 4.20. PCI_SELFID register

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Table 4.56. PCI_SELFID register format

BitsDescription
[31:5]

Reserved. Use read-modify-write to preserve value.

[4:0]Contains the slot location of the baseboard on the PCI backplane.

PCI_FLAGS register

This read-only register returns status information about abort conditions on the PCI bus. The register format is shown in Figure 4.21 and Table 4.57.

Figure 4.21. PCI_FLAGS register

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Table 4.57. PCI_FLAGS register format

BitsDescription
[31:3]

Reserved.

[2]Set this bit to enable aborts. Clear the bit to mask aborts.
[1]Initiator abort flag. The bit value is the same as bit 39 of the Command Status Register in the Xilinx PCI controller. This bit will be HIGH if an error occurred while the baseboard was operating as a master.
[0]Target abort flag. The bit value is the same as bit 38 of the Command Status Register in the Xilinx PCI controller. This bit position is reserved for future use.

PCI_SMAPx registers

The map registers relate to the PCI Base Address Registers (BAR) specified in the PCI Local Bus Specification.

Two remap registers provide the base addresses (bits [31:28] of the FPGA internal bus) for remapping PCI accesses to two 256MB blocks of memory. A third remap register provides the base address (bits [31:24] of the FPGA internal bus) for remapping PCI accesses to a 16MB block of I/O.

An example of memory remapping as shown in Figure 4.22:

  1. The PCI controller has been configured to react to addresses in the range 0x40000000 to 0x4FFFFFFF as belonging to target region 1.

  2. A master on the PCI bus drives 0x41234567 onto the bus.

  3. In this example, PCI_SMAP1 contains 0x80000000. The most significant four bits of the incoming PCI address are replaced with b1000.

  4. The modified address is output onto the EB bus. In this case, the EB address is 0x81234567.

  5. The EB processes the transaction.

    Note

    The SMAP registers decode both external I/O and memory requests. That is, any external access to the specified address range is converted into an AHB or AXI transfer for the mapped baseboard address.

    The memory controller might process the I/0 and memory accesses differently however. For example, a memory read might use prefetched data, but an I/O read would generate a single memory read at the time the access was received.

Figure 4.22. PCI to baseboard mapping

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The memory base address remap register format is shown in Figure 4.23 and Table 4.58.

Figure 4.23. memory remap register

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Table 4.58. memory remap register format

BitsDescription
[31:28]

Contains the value to use for address bits [31:28] when the PCI accesses the baseboard slave port associated with a PCI memory region.

[27:0]

Reserved.


The I/O base address remap register format is shown in Figure 4.24 and Table 4.59.

Figure 4.24. I/O remap register

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Table 4.59. I/O remap register format

BitsDescription
[31:24]

Contains the value to use for address bits [31:24] when the PCI accesses the baseboard slave port associated with the PCI I/O region.

[23:0]

Reserved.


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